Texas Instruments TMS320DM646x User Manual page 58

Architecture
The EMAC write to the completion pointer actually stores the value in the state RAM. The CPU written
value does not actually change the register value. The host written value is compared to the register
content (which was written by the EMAC) and if the two values are equal then the interrupt is removed;
otherwise, the interrupt remains asserted. The host may process multiple packets prior to
acknowledging an interrupt, or the host may acknowledge interrupts for every packet.
2.16.1.4 Statistics Interrupt
The statistics level interrupt (STATPEND) is issued when any statistics value is greater than or equal to
8000 0000h, if enabled by setting the STATMASK bit in the MAC interrupt mask set register
(MACINTMASKSET) to 1. The statistics interrupt is removed by writing to decrement any statistics
value greater than 8000 0000h. As long as the most-significant bit of any statistics value is set, the
interrupt remains asserted.
2.16.1.5 Host Error Interrupt
The host error interrupt (HOSTPEND) is issued, if enabled, under error conditions dealing with the
handling of buffer descriptors, detected during transmit or receive DMA transactions. The failure of the
software application to supply properly formatted buffer descriptors results in this error. The error bit
can only be cleared by resetting the EMAC module in hardware.
The host error interrupt is enabled by setting the HOSTMASK bit in the MAC interrupt mask set register
(MACINTMASKSET) to 1. The host error interrupt is disabled by clearing the appropriate bit in the MAC
interrupt mask clear register (MACINTMASKCLEAR) to 0. The raw and masked host error interrupt
status may be read by reading the MAC interrupt status (unmasked) register (MACINTSTATRAW) and
the MAC interrupt status (masked) register (MACINTSTATMASKED), respectively.
The transmit host error conditions are:
SOP error
Ownership bit not set in SOP buffer
Zero next buffer descriptor pointer with EOP
Zero buffer pointer
Zero buffer length
Packet length error
The receive host error conditions are:
Ownership bit not set in input buffer
Zero buffer pointer
58 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
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SPRUEQ6 – December 2007
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