Emac Control Module Interrupts - Texas Instruments TMS320DM646x User Manual

Architecture
2.6.3 Interrupt Control
The EMAC control module combines multiple interrupt conditions generated by the EMAC and MDIO
modules into four separate interrupt signals
interrupt controller. The four separate sources of interrupt can be individually enabled for each channel by
the CMRXTHRESHINTEN, CMRXINTEN, CMTXINTEN, and CMMISCINTEN registers.
2.6.3.1 Transmit Pulse Interrupt
The EMAC control module receives the eight individual transmit interrupts originating from the EMAC
module, one for each of the eight channels, and combines them into a single transmit pulse interrupt to
the CPU. This transmit pulse interrupt is paced, as described in
transmit pending interrupt(s) are selected at the EMAC control module level, by setting one or more bits in
the EMAC control module transmit interrupt enable register (CMTXINTEN). The masked interrupt status
can be read in the EMAC control module transmit interrupt status register (CMTXINTSTAT).
Upon reception of a transmit pulse interrupt, the ISR performs the following:
1. Read CMTXINTSTAT to determine which channel(s) caused the interrupt.
2. Process received packets for the interrupting channel(s).
3. Write the appropriate CPGMAC transmit channel n completion pointer register(s) (TXnCP) with the
address of the last buffer descriptor of the last packet processed by the application software.
4. Write the MAC end of interrupt vector register (MACEOIVECTOR) in the EMAC module with a value of
2h to signal the end of the transmit interrupt processing.
2.6.3.2 Receive Pulse Interrupt
The EMAC control module receives the eight individual receive interrupts originating from the EMAC
module, one for each of the eight channels, and combines them into a single receive pulse interrupt to the
CPU. This receive pulse interrupt is paced, as described in
pending interrupt(s) are selected at the EMAC control module level, by setting one or more bits in the
EMAC control module receive interrupt enable register (CMRXINTEN). The masked interrupt status can
be read in the EMAC control module receive interrupt status register (CMRXINTSTAT).
Upon reception of a receive pulse interrupt, the ISR performs the following:
1. Read CMRXINTSTAT to determine which channel(s) caused the interrupt.
2. Process received packets for the interrupting channel(s).
3. Write the appropriate CPGMAC receive channel n completion pointer register(s) (RXnCP) with the
address of the last buffer descriptor of the last packet processed by the application software.
4. Write the MAC end of interrupt vector register (MACEOIVECTOR) in the EMAC module with a value of
1h to signal the end of the receive interrupt processing.
32 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
(Table
Table 5. EMAC Control Module Interrupts
ARM Event Acronym
24 MAC_RXTH
25 MAC_RX
26 MAC_TX
27 MAC_MISC
5) that are mapped to a CPU interrupt via the CPU
Source
EMAC receive threshold
EMAC receive
EMAC transmit
EMAC miscellaneous
Section 2.6.4. The eight individual
Section 2.6.4. The eight individual receive
www.ti.com
SPRUEQ6 – December 2007
Submit Documentation Feedback