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5.22 Receive Unicast Enable Set Register (RXUNICASTSET)
The receive unicast enable set register (RXUNICASTSET) is shown in
Table
61.
Figure 62. Receive Unicast Enable Set Register (RXUNICASTSET)
31
15
7
6
RXCH7EN
RXCH6EN
R/W1S-0
R/W1S-0
LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset
Table 61. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
Bit
Field
Value
31-8
Reserved
0
7
RXCH7EN
0-1
6
RXCH6EN
0-1
5
RXCH5EN
0-1
4
RXCH4EN
0-1
3
RXCH3EN
0-1
2
RXCH2EN
0-1
1
RXCH1EN
0-1
0
RXCH0EN
0-1
SPRUEQ6 – December 2007
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Reserved
Reserved
5
4
RXCH5EN
RXCH4EN
R/W1S-0
R/W1S-0
Description
Reserved
Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Ethernet Media Access Controller (EMAC) Registers
Figure 62
R-0
R-0
3
2
RXCH3EN
RXCH2EN
R/W1S-0
R/W1S-0
and described in
16
8
1
0
RXCH1EN
RXCH0EN
R/W1S-0
R/W1S-0
105