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Figure 21-44. Proper Positioning of Receive Frame-sync Pulses
21.4.4.4 Underflow in the Receiver
The McBSP module indicates a receiver underflow condition by setting the
McBSPi.MCBSPLP_IRQSTATUS_REG[4] RUNDFLSTAT bit. This error occurs when sDMA controller or
MPU/IVA2.2 subsystem reads data from an empty RB this happens only if the MPU/IVA2.2 subsystem or
sDMA controller does not respect the DMA length, does not wait for DMA request, or does not check the
buffer status before reading data. According to the
settings this condition can generate the McBSPi_IRQ line to be asserted low. Writing 1 to the
corresponding bit in
21.4.4.5 Underflow in the Transmitter
The McBSP module indicates a transmitter empty (or underflow) condition by setting the
McBSPi.MCBSPLP_IRQSTATUS_REG[11] XUNDFLSTAT bit. Also the legacy mode
McBSPi.MCBSPLP_SPCR2_REG[2] XEMPTY bit is cleared. Either of the following events activates
XEMPTY bit (XEMPTY = 0):
•
McBSPi.MCBSPLP_DXR_REG
the XSR have been shifted out on the mcbspi_dx pin.
•
The transmitter is reset (by forcing McBSPi.MCBSPLP_SPCR2_REG[0] XRST=0, or by an global
reset) and is then restarted.
XEMPTY bit is deactivated (XEMPTY=1) when a new word in
transferred to Transmit Buffer (XB). If McBSPi.MCBSPLP_PCR_REG[11] FSXM=1 and
McBSPi.MCBSPLP_SRGR2_REG[12] FSGM=0, the transmit frame-sync signal (FSX) is generated when
Transmit Buffer (XB) is not empty. When McBSPi.MCBSPLP_SRGR2_REG[12] FSGM=0,
McBSPi.MCBSPLP_SRGR2_REG[11:0] FPER and McBSPi.MCBSPLP_SRGR1_REG[15:8] FWID are
used to determine the frame-synchronization period and width (external FSX is gated by the buffer empty
condition). Otherwise, the transmitter waits for the next frame-synchronization pulse before sending out
the next frame on mcbspi_dx.
When the transmitter is taken out of reset (McBSPi.MCBSPLP_SPCR2_REG[0] XRST=1), it is in a
transmitter ready state (McBSPi.MCBSPLP_SPCR2_REG[1] XRDY bit =1) and transmitter empty
(McBSPi.MCBSPLP_SPCR2_REG[2] XEMPTY=0) state. If
SWPU177N – December 2009 – Revised November 2010
Public Version
For 2-bit delay:
Next frame-sync pulse
here or later is OK.
For 1-bit delay:
Next frame-sync pulse
here or later is OK.
CLKR
FSR
DR
Last bit of
current frame
McBSPi.MCBSPLP_IRQSTATUS_REG
has not been loaded and XB is empty, and all bits of the data word in
Copyright © 2009–2010, Texas Instruments Incorporated
For 0-bit delay:
Next frame-sync pulse
here or later is OK.
Earliest possible time
to begin transfer of
next frame
mcbsp-039
McBSPi.MCBSPLP_IRQENABLE_REG
register clears the interrupt.
McBSPi.MCBSPLP_DXR_REG
McBSPi.MCBSPLP_DXR_REG
Multi-Channel Buffered Serial Port
McBSP Functional Description
register
is
is loaded by
3111
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