Dual Channel Chip Select Routing; Dual Channel Chip Select Routing Guidelines - Intel Xeon Design Manual

Intel
3.2.4

Dual Channel Chip Select Routing

The MCH provides eight chip select signals. Two chip selects must be routed to each DIMM (one
for each side). Chip selects for each DIMM must be length matched to the corresponding clock
within ± 875 mils and require parallel termination resistors (Rtt) to DDR VTERM.
Table 11. Dual Channel Chip Select Routing Guidelines
Parameter
Signal Group
Topology
Reference Plane
Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing
MCH to DIMM1 Trace
Length
MCH to DIMM2 Trace
Length
MCH to DIMM3 Trace
Length
MCH to DIMM4 Trace
Length
Trace Length - DIMM to
Rtt
Termination Resistor
(Rtt)
MCH Breakout
Guidelines
NOTES:
1. No length tuning required.
2. See the Intel
Platform Design Guide Addendum
®
Xeon™ Processor and Intel
1-DIMM Solution
0°, 25°, 90°
1,2
50 Ω ± 10%
5 mils
15 mils
3.0" to 4.0"
Not Applicable
Not Applicable
Not Applicable
0.3" to 1.5"
39.2 Ω ± 1%
5/5, < 500 mils
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform
2-DIMM Solution
25°
CS[7:0]#
Point to Point
Ground
50 Ω ± 10%
5 mils
15 mils
3.0" to 4.0"
4.0" to 6.0"
Not Applicable
Not Applicable
0.3" to 1.5"
39.2 Ω ± 1%
5/5, < 500 mils
®
E7500/E7501 Chipset Compatible Platform Design Guide.
2-DIMM Solution
Reference
90°
50 Ω ± 10%
5 mils
15 mils
3.0" to 4.0"
Note 2
4.0" to 6.0"
Not Applicable
Not Applicable
0.3" to 1.5"
39.2 Ω ± 1%
5/5, < 500 mils
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