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DS-30X interface
Table 46
Digital Pad – values and offset allocations (Part 1 of 2)
PAD SET 0
Offset
0
1
2
3
553-3023-211 Standard 1.00 June 2001
NTAK79 2.0 Mb PRI card
•
8031 microcontroller
•
Card-LAN / echo / test port interface
The NTAK79 interfaces to one DS-30X bus which contains 32 byte-
interleaved timeslots operating at 2.56 Mb. Each timeslot contains 10 bits
in A10 message format; eight are assigned to voice/data (64 kbps), one to
signaling (8 kbps), and one is a data valid bit (8 kbps).
The incoming serial bit stream is converted to 8-bit parallel bytes to be
directed to padding control.
The signaling bits are extracted and inserted by the A07 signaling interface
circuitry. The DS-30X timeslot number is mapped to the PCM-30 channel
number. Timeslots 0 and 16 are currently unused for PCM.
Digital PAD
Software selects A-Law or Mu-Law and one of 32 possible PAD values for
each channel. These values are provided in a PROM through which the data
is routed. The idle code for A-Law is 54H and for Mu-Law is 7FH. The
unequipped code is FFH for both A-Law and Mu-Law. As the idle code and
unequipped code can be country dependent, the software instructs the
NTAK79 to use different codes for each direction. The 32 digital pads
available are listed in Table 46. The values shown are attenuation levels;
1.0 dB is 1 dB of loss and –1.0 dB is 1 dB of gain.
PAD
0.6 dB
1.0 dB
2.0 dB
3.0 dB
PAD SET 1
Offset
0
1
2
3
PAD
0.0 dB
–1.0 dB
–2.0 dB
–3.0 dB