Note: Clocking slips can occur between Media Gateways that are
clocked from different COs, if the COs are not synchronized. The slips
can cause degraded voice quality.
Clock rate converter
The 1.5 Mb clock is generated by a Phase-Locked Loop (PLL). The PLL
synchronizes the 1.5 Mb DS1 clock to the 2.56 Mb system clock through the
common multiple of 8 kHz by using the main frame synchronization signal.
Succession Communication Server for Enterprise 1000 Circuit Card Reference Guide
NTRB21 DTI/PRI/DCH TMDI card
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