Architecture; Ds-30X Interface - Nortel Enterprise 1000 Reference Manual

Page 160 of 236

Architecture

DS-30X interface

553-3023-211 Standard 1.00 June 2001
NTBK50 2.0 Mb PRI card
The main functional blocks of the NTBK50 architecture are:
• DS-30X interface
• A07 signaling interface
• digital pad
• carrier interface
• CEPT transceiver
• SLIP control
• D-channel support interface
• clock controller interface
• Card-LAN / echo / test port interface
• 80C51FA Microcontroller
NTBK50 interfaces to one DS-30X bus which contains 32-byte interleaved
timeslots operating at 2.56 Mb. Each timeslot contains 10 bits in A10
message format; eight are assigned to voice/data (64 Kbps), one to signaling
(8 Kbps), and one is a data valid bit (8 Kbps).
The incoming serial bit stream is converted to 8-bit parallel bytes to be
directed to padding control. The signaling bits are extracted and inserted by
the A07 signaling interface circuitry. Timeslots 0 and 16 are currently unused
for PCM.
Digital PAD
The software selects A-Law or Mu-Law and one of 32 possible PAD values
for each channel. These values are provided in a PROM through which the
data is routed. The idle code for A-Law is 54H and for Mu-Law is 7FH. The
unequipped code is FFH for both A-Law and Mu-Law.
As the idle code and unequipped code can be country dependent, the software
instructs the NTBK50 to use different codes for each direction. The 32 digital