Functional Description; Phase Difference Detector Circuit; Digital Phase Lock Loops - Nortel Enterprise 1000 Reference Manual

Functional description

Phase difference detector circuit

Digital phase lock loops

Succession Communication Server for Enterprise 1000 Circuit Card Reference Guide
NTAK20 clock controller daughterboard
The main functional blocks of the NTAK20 architecture include:
•

phase difference detector circuit

• digital Phase Locked Loop (PLL)
• clock detection circuit
• digital-to-analog converter
• CPU MUX bus interface
• signal conditioning drivers and buffers
• sanity timer
• microprocessor
• CPU interface
• external timing interface
This circuit, under firmware control, allows a phase difference measurement
to be taken between the reference entering the PLL and the system clock.
The phase difference is used for making frequency measurements, and
evaluating input jitter and PLL performance.
The main digital PLL enables the clock controller to provide a system clock
to the CPU. This clock is both phase and frequency locked to a known
incoming reference.
The hardware has a locking range of + 4.6 ppm for Stratum 3 and + 50 ppm
for Stratum 4 (CCITT).
A second PLL on the clock controller provides the means for monitoring
another reference. Note that the error signal of this PLL is routed to the phase
difference detector circuit so the microprocessor can process it.
Page 29 of 236