Sleep Mode Timing; Gpio Reset Timing; Gpio Reset Timing Specifications - Intel PXA255 Datasheet

Figure 5. GPIO Reset Timing
nRESET_OUT
Table 17. GPIO Reset Timing Specifications
Symbol
tA_GP[1]
tDHW_OUT_A
tDHW_OUT
tDHW_OUT_F
tDHW_NCS0
NOTES:
1. GP[1] is not recognized as a reset source again until configured to do so in software. Software should
check the state of GP[1] before configuring as a reset to ensure no spurious reset is generated.
2. Time is 512*N processor clock cycles plus up to 4 cycles of the 3.6864-MHz input clock.
3. Time during the frequency change sequence depends on the state of the PLL lock detector at the
assertion of GPIO reset. The lock detector has a maximum time of 350µs plus synchronization.
4.7.5

Sleep Mode Timing

Sleep mode is asserted internally; and asserts the nRESET_OUT and PWR_EN signals. The
sequence indicated in
Mode Timing Specifications" on page 34
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
t
A_GP[1]
GP[1]
t
DHW_OUT_A
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is
deasserted or the application processor will enter Sleep Mode
Description
Minimum assert time of GP[1]
3.6864MHz input clock cycles
Delay between GP[1] asserted and
nRESET_OUT asserted in 3.6864 MHz
input clock cycles
Delay between nRESET_OUT asserted
and nRESET_OUT de-asserted, run or
2
turbo mode
Delay between nRESET_OUT asserted
and nRESET_OUT de-asserted, during
frequency change sequence
Delay between nReset_Out de-asserted
and nCS0 asserted
Figure 6, "Sleep Mode Timing" on page 34
t
DHW_OUT
Min
1
in
4
3
1.28
1.28
3
150.69
and detailed in
is the required timing parameters for sleep mode.
Electrical Specifications
Typical Max Units
cycles
8 cycles
6.5 µs
µs
360
— 390 ns
Figure 18, "Sleep
33