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5. When the host completes its download, the host must wait a minimum of 15 TCKs, then
switch the JTAG IR to DBGRX, and complete the handshaking (by scanning in a value that
sets DBG_SR[35]). This clears TXRXCTL[31] and allows the debug handler code to exit the
polling loop.
6. After the handler exits the polling loop, it branches to the downloaded code.
Note: The debug handler stub must reside in the instruction cache and execute out of the cache while
doing the synchronization. The processor must not be doing any code fetches to external memory
while code is being downloaded.
10.13.5.1
Dynamic Code Download Synchronization
The following pieces of code are necessary in the debug handler to implement the synchronization
used during dynamic code download. The pieces must be ordered in the handler as shown below.
# Before the download can start, all outstanding instruction fetches must complete.
# The MCR invalidate IC by line function serves as a barrier instruction in
# the core. All outstanding instruction fetches are guaranteed to complete before
# the next instruction executes.
# NOTE1: the actual address specified to invalidate is implementation defined, but
# must not have any harmful effects.
# NOTE2: The placement of the invalidate code is implementation defined, the only
# requirement is that it must be placed such that by the time the debugger starts
# loading the instruction cache, all outstanding instruction fetches have completed
mov r5, address
mcr p15, 0, r5, c7, c5, 1
# The host waits for the debug handler to signal that it is ready for the
# code download. This can be done using the TX register access handshaking
# protocol. The host polls the TR bit through JTAG until it is set, then begins
# the code download. The following MCR does a write to TX, automatically
# setting the TR bit.
# NOTE: The value written to TX is implementation defined.
mcr p14, 0, r6, c8, c0, 0
# The debug handler waits until the download is complete before continuing. The
# debugger uses the RX handshaking to signal the debug handler when the download
# is complete. The debug handler polls the RR bit until it is set. A debugger write
# to RX automatically sets the RR bit, allowing the handler to proceed.
# NOTE: The value written to RX by the debugger is implementation defined - it can
be a bogus value signalling the handler to continue or it can be a target address
for the handler to branch to.
loop:
mrc
bpl
mrc
bx
In a very simple debug handler stub, the above parts may form the complete handler downloaded
during reset (with some handler entry and exit code). When a debug exception occurs, routines can
be downloaded as necessary. This allows the entire handler to be dynamic.
Intel® XScale™ Microarchitecture User's Manual
p14, 0, r15, c14, c0, 0
loop
p14, 0, r0, c8, c0, 0
r0
@ handler waits for signal from debugger
@ debugger writes target address to RX
Software Debug
10-39
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