Register 1: Control & Auxiliary Control Registers - Intel PXA255 User Manual

Table 7-5. Cache Type Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0
reset value: As Shown
Bits
31:29
28:25
24
23:21
20:18
17:15
14
13:12
11:9
8:6
5:3
2
1:0
7.2.2 Register 1: Control & Auxiliary Control Registers
Register 1 is made up of two registers, one that is compliant with ARM* Version 5 and referred by
opcode_2 = 0x0, and the other which is specific to the Intel® XScale™ core is referred by
opcode_2 = 0x1. The latter is known as the Auxiliary Control Register.
The Exception Vector Relocation bit (bit 13 of the ARM* control register) allows the vectors to be
mapped into high memory rather than their default location at address 0. This bit is readable and
writable by software. If the MMU is enabled, the exception vectors will be accessed via the usual
translation method involving the PID register (see
page 7-12) and the TLBs. To avoid automatic application of the PID to exception vector accesses,
software may relocate the exceptions to high memory.
Intel® XScale™ Microarchitecture User's Manual
Access
Read-as-Zero / Write Ignored
Read / Write Ignored
Read / Write Ignored
Read-as-Zero / Write Ignored
Read / Write Ignored
Read / Write Ignored
Read-as-Zero / Write Ignored
Read / Write Ignored
Read-as-Zero / Write Ignored
Read / Write Ignored
Read / Write Ignored
Read-as-Zero / Write Ignored
Read / Write Ignored
8
Description
Reserved
Cache class = 0b0101
The caches support locking, write back and round-robin
replacement. They do not support address by index.
Harvard Cache = 1
Reserved
Data Cache Size
0b110 = 32 kB
Data cache associativity = 0b101 = 32
Reserved
Data cache line length = 0b10 = 8 words/line
Reserved
Instruction cache size
0b110 = 32 kB
Instruction cache associativity = 0b101 = 32
Reserved
Instruction cache line length = 0b10 = 8 words/line
Section 7.2.11, "Register 13: Process ID" on
Configuration
7 6 5 4 3 2 1 0
7-5