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Data Cache
6.2.3.4
Write-Back Versus Write-Through
The Intel® XScale™ core supports write-back caching or write-through caching, controlled
through the MMU page attributes. When write-through caching is specified, all store operations are
written to external memory even if the access hits the cache. This feature keeps the external
memory coherent with the cache, i.e., no dirty bits are set for this region of memory in the data/
mini-data cache. This however does not guarantee that the data/mini-data cache is coherent with
external memory, which is dependent on the system level configuration, specifically if the external
memory is shared by another master.
When write-back caching is specified, a store operation that hits the cache will not generate an
immediate write to external memory, waiting instead for round-robin eviction or cache cleaning to
write the data into external memory. Thus write-back caching is typically preferred for
performance as it reduces external memory write traffic.
6.2.4
Round-Robin Replacement Algorithm
The line replacement algorithm for the data cache is round-robin. Each set in the data cache has a
round-robin pointer that keeps track of the next line (in that set) to replace. The next line to replace
in a set is the next sequential line after the last one that was just filled. For example, if the line for
the last fill was written into way 5-set 2, the next line to replace for that set would be way 6. None
of the other round-robin pointers for the other sets are affected when they are not the sets being
accessed.
After reset, way 31 is pointed to by the round-robin pointer in each of the sets. Once a line is
written into way 31, the round-robin pointer points to the first available way of a set, beginning
with way 0 if no lines have been re-configured as data RAM in that particular set. Re-configuring
lines as data RAM effectively reduces the available lines for cache updating. For example, if the
first three lines of a set were re-configured, the round-robin pointer would point to the line at way 3
after it rolled over from way 31. Refer to
RAM"
for more details on data RAM.
The mini-data cache follows the same round-robin replacement algorithm as the data cache except
that there are only two lines the round-robin pointer can point to such that the round-robin pointer
always points to the least recently filled line. A least recently used replacement algorithm is not
supported because the purpose of the mini-data cache is to cache data that exhibits low temporal
locality, i.e.,data that is placed into the mini-data cache is typically modified once and then written
back out to external memory. Examples of data items that should be streamed through the mini data
cache for improved system performance might be a audio or video bit stream such as MP3 or
MPEG-4 data.
6.2.5
Parity Protection
The data cache and mini-data cache are protected by parity to ensure data integrity; there is one
parity bit per byte of data. (The tags are NOT parity protected.) When a parity error is detected on a
data/mini-data cache access, a data abort exception occurs. Before servicing the exception,
hardware will set bit 10 of the Fault Status Register.
A data/mini-data cache parity error is an imprecise data abort, meaning R14_ABORT (+8) may not
point to the instruction that caused the parity error. If the parity error occurred during a load, the
targeted register may be updated with incorrect data.
6-6
Section 6.4, "Re-configuring the Data Cache as Data
Intel® XScale™ Microarchitecture User's Manual
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