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Software Debug
10.13.5
Dynamically Loading IC After Reset
An external host can load code into the instruction cache "on the fly" or "dynamically". This
occurs when the host downloads code while the processor is not being reset. However, this requires
strict synchronization between the code running on the Intel® XScale™ core and the external host.
The guidelines for downloading code during program execution must be followed to ensure proper
operation of the processor. The description in this section focuses on using a debug handler running
on the Intel® XScale™ core to synchronize with the external host, but the details apply for any
application that is running while code is dynamically downloaded.
To dynamically download code during software debug, there must be a minimal debug handler
stub, responsible for doing the handshaking with the host, resident in the instruction cache. This
debug handler stub can be downloaded into the instruction cache during processor reset using the
method described in
describes the details for implementing the handshaking in the debug handler.
Figure 10-13
dynamic code download.
Figure 10-13. Downloading Code in IC During Program Execution
Debugger Actions
JTAG IR
Handler begins execution
Debug Handler Actions
The following steps describe the details for downloading code:
1. Since the debug handler is responsible for synchronization during the code download, the
handler must be executing before the host can begin the download. The debug handler
execution starts when the application running on the Intel® XScale™ core generates a debug
exception or when the host generates an external debug break.
2. While the DBGTX JTAG instruction is in the JTAG IR (see
Command"), the host polls DBG_SR[0], waiting for the debug handler to set it.
3. When the debug handler gets to the point where it is ready to begin the code download, it
writes to TX, which automatically sets DBG_SR[0]. This signals the host that it can begin the
download. The debug handler then begins polling TXRXCTRL[31] waiting for the host to
clear it through the DBGRX JTAG register (to indicate the download is complete).
4. The host writes LDIC to the JTAG IR, and downloads the code. For each line downloaded, the
host must invalidate the target line before downloading code to that line. Failure to invalidate a
line prior to writing it will cause unpredictable operation by the processor.
10-38
Section
10.13.4.
Section 10, "Dynamic Code Download Synchronization"
shows a high level view of the actions taken by the host and debug handler during
wait for handler to signal
ready to start download
DBGTX
signal host ready
for download
download code
LDIC
wait for host to signal
download complete
Section 10, "DBGTX JTAG
Intel® XScale™ Microarchitecture User's Manual
signal handler
download is complete
clock
15 TCKs
DBGRX
continue execution.
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