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Table 7-23. PWRMODE Register 7
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: writable bits set to 0
Bits
31:2
1:0
Software can change core clock frequency by writing to CP 14 register 6, CCLKCFG.
Table 7-24. CCLKCFG Register 6
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:4
3:0
Table 7-25. Clock and Power Management valid operations
Enter Sleep Mode
Read CCLKCFG
Write CCLKCFG
7.3.3
Registers 8-15: Software Debug
Software debug is supported by address breakpoint registers (Coprocessor 15, register 14), serial
communication over the JTAG interface and a trace buffer. Registers 8 and 9 are used for the serial
interface and registers 10 through 13 support a 256 entry trace buffer. Register 14 and 15 are the
debug link register and debug SPSR (saved program status register). These registers are explained
in more detail in
Opcode_2 and CRm must be zero.
Intel® XScale™ Microarchitecture User's Manual
Access
Read-unpredictable / Write-as-Zero
Read / Write
Access
Read-unpredictable / Write-as-Zero
Read / Write
Function
Enter Idle Mode
Reserved
Chapter 10, "Software
Reserved
Mode (M)
0 = ACTIVE
1 = Idle Mode
2 = Reserved
3 = Sleep Mode
Reserved
Core Clock Configuration (CCLKCFG)
0b0001 - Enter Turbo Mode
0b001x - Enter Frequency Change Sequence (Turbo
Mode bit may be set or cleared in the same write)
Other values are reserved
Data
1
2
3
ignored
CCLKCFG value
Debug".
Configuration
8
7
6
5
4
3
2
Description
8
7
6
5
4
3
2
CCLKCFG
Description
Instruction
MCR p14, 0, Rd, c7, c0, 0
MCR p14, 0, Rd, c7, c0, 0
MCR p14, 0, Rd, c7, c0, 0
MRC p14, 0, Rd, c6, c0, 0
MCR p14, 0, Rd, c6, c0, 0
1
0
M
1
0
7-17
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