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Super X11DSC+ User's Manual
DIMM Population Requirements for the Intel®
81xx/61xx/51xx/41xx/31xx Series Processors
For optimal memory performance, follow the tables below when populating memory modules.
Memory Population Table for the X11DP Motherboard w/24 DIMM Slots Onboard
When 1 CPU is used:
1 CPU & 1 DIMM
1 CPU & 2 DIMMs
1 CPU & 3 DIMMs
1 CPU & 4 DIMMs
1 CPU & 5 DIMMs
(Unbalanced: not recom-
mended)
1 CPU & 6 DIMM
1 CPU & 7 DIMMs
(Unbalanced: not recom-
mended)
1 CPU & 8 DIMMs
1 CPU & 9 DIMMs
(Unbalanced: not recom-
mended)
1 CPU & 10 DIMMs
(Unbalanced: not recom-
mended)
1 CPU & 11 DIMMs
(Unbalanced: not recom-
mended)
1 CPU & 12 DIMMs
When 2 CPUs are used:
2 CPUs & 2 DIMMs
2 CPUs & 4 DIMMs
2 CPUs & 6 DIMMs
2 CPUs & 8 DIMMs
2 CPUs & 10 DIMMs
2 CPUs & 12 DIMMs
2 CPUs & 14 DIMMs
2 CPUs & 16 DIMMs
2 CPUs & 18 DIMMs
2 CPUs & 20 DIMMs
2 CPUs & 22 DIMMs
(Unbalanced: not recom-
mended)
2 CPUs & 24 DIMMs
Memory Population Sequence
CPU1: P1-DIMMA1
CPU1: P1-DIMMA1/P1-DIMMD1
CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1
CPU1: P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1
CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1
CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1/P1-DIMMF1
CPU1: P1-DIMMB1/P1-DIMMB2/P1-DIMMA1/P1-DIMMA2/P1-DIMMD1/P1-DIMME1/P1-DIMMF1
CPU1: P1-DIMMB1/P1-DIMMB2/P1-DIMMA1/P1-DIMMA2/P1-DIMMD2/P1-DIMMD1/P1-DIMME2/P1-DIMME1
CPU1: P1-DIMMC1/P1-DIMMC2/P1-DIMMB1/P1-DIMMB2/P1-DIMMA1/P1-DIMMA2/
P1-DIMMD1/P1-DIMME1/P1-DIMMF1
CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMB2/P1-DIMMA1/P1-DIMMA2/
P1-DIMMD2/P1-DIMMD1/P1-DIMME2/P1-DIMME1/P1-DIMMF1
CPU1: P1-DIMMC1/P1-DIMMC2/P1-DIMMB1/P1-DIMMB2/P1-DIMMA1/P1-DIMMA2/
P1-DIMMD2/P1-DIMMD1/P1-DIMME2/P1-DIMME1/P1-DIMMF1
CPU1: P1-DIMMC1/P1-DIMMC2/P1-DIMMB1/P1-DIMMB2/P1-DIMMA1/P1-DIMMA2/
P1-DIMMD2/P1-DIMMD1/P1-DIMME2/P1-DIMME1/P1-DIMMF2/P1-DIMMF1
Memory Population Sequence
CPU1: P1-DIMMA1
CPU2: P2-DIMMA1
CPU1: P1-DIMMA1/P1-DIMMD1
CPU2: P2-DIMMA1/P2-DIMMD1
CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1
CPU2: P2-DIMMC1/P2-DIMMB1/P2-DIMMA1
CPU1: P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1
CPU2: P2-DIMMB1/P2-DIMMA1/P2-DIMMD1/P2-DIMME1
CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1/P1-DIMMF1
CPU2: P2-DIMMB1/P2-DIMMA1/P2-DIMMD1/P2-DIMME1
CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1/P1-DIMMF1
CPU2: P2-DIMMC1/P2-DIMMB1/P2-DIMMA1/P2-DIMMD1/P2-DIMME1/P2-DIMMF1
CPU1: P1-DIMMB1/P1-DIMMB2/P1-DIMMA1/P1-DIMMA2/P1-DIMMD2/P1-DIMMD1/P1-DIMME2/P1-DIMME1
CPU2: P2-DIMMC1/P2-DIMMB1/P2-DIMMA1/P2-DIMMD1/P2-DIMME1/P2-DIMMF1
CPU1: P1-DIMMB1/P1-DIMMB2/P1-DIMMA1/P1-DIMMA2/P1-DIMMD2/P1-DIMMD1/P1-DIMME2/P1-DIMME1
CPU2: P2-DIMMB1/P2-DIMMB2/P2-DIMMA1/P2-DIMMA2/P2-DIMMD2/P2-DIMMD1/P2-DIMME2/P2-DIMME1
CPU1: P1-DIMMC1/P1-DIMMC2/P1-DIMMB1/P1-DIMMB2/P1-DIMMA1/P1-DIMMA2/P1-DIMMD2/P1-DIMMD1/
P1-DIMME2/P1-DIMME1/P1-DIMMF2/P1-DIMMF1
CPU2: P2-DIMMC1/P2-DIMMB1/P2-DIMMA1/P2-DIMMD1/P2-DIMME1/P2-DIMMF1
CPU1: P1-DIMMC1/P1-DIMMC2/P1-DIMMB1/P1-DIMMB2/P1-DIMMA1/P1-DIMMA2/P1-DIMMD2/P1-DIMMD1/
P1-DIMME2/P1-DIMME1/P1-DIMMF2/P1-DIMMF1
CPU2: P2-DIMMB1/P2-DIMMB2/P2-DIMMA1/P2-DIMMA2/P2-DIMMD2/P2-DIMMD1/P2-DIMME2/P2-DIMME1
CPU1: P1-DIMMC1/P1-DIMMC2/P1-DIMMB1/P1-DIMMB2/P1-DIMMA1/P1-DIMMA2/
P1-DIMMD2/P1-DIMMD1/P1-DIMME2/P1-DIMME1/P1-DIMMF1
CPU2: P2-DIMMC1/P2-DIMMC2/P2-DIMMB1/P2-DIMMB2/P2-DIMMA1/P2-DIMMA2/
P2-DIMMD2/P2-DIMMD1/P2-DIMME2/P2-DIMME1/P2-DIMMF1
CPU1: P1-DIMMC1/P1-DIMMC2/P1-DIMMB1/P1-DIMMB2/P1-DIMMA1/P1-DIMMA2/
P1-DIMMD2/P1-DIMMD1/P1-DIMME2/P1-DIMME1/P1-DIMMF2/P1-DIMMF1
CPU2: P2-DIMMC1/P2-DIMMC2/P2-DIMMB1/P2-DIMMB2/P2-DIMMA1/P2-DIMMA2/
P2-DIMMD2/P2-DIMMD1/P2-DIMME2/P2-DIMME1/P2-DIMMF2/P2-DIMMF1
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