Rstctl_Hardreset_Stat Register; Rstctl_Hardreset_Stat Register Description - Texas Instruments SimpleLink MSP432P4 Series Technical Reference Manual

RSTCTL Registers
3.3.2 RSTCTL_HARDRESET_STAT Register (offset = 04h)
Hard Reset Status Register
31 30 29 28
r r r r
15 14 13 12
SRC1 SRC1 SRC1 SRC1
5 4 3 2
r-(0) r-(0) r-(0) r-(0)
Bit Field
31-16 Reserved
15 SRC15
14 SRC14
13 SRC13
12 SRC12
11 SRC11
10 SRC10
9 SRC9
8 SRC8
7 SRC7
6 SRC6
5 SRC5
4 SRC4
3 SRC3
2 SRC2
1 SRC1
0 SRC0
(1)
Refer to the device-specific data sheet for the mapping of device-level Hard Reset sources to the appropriate bit in this register.
260
Reset Controller (RSTCTL)
Figure 3-3. RSTCTL_HARDRESET_STAT Register
27 26 25 24
r r r
11 10 9
SRC1 SRC1 SRC9 SRC8
1 0
r-(0) r-(0) r-(0) r-(0)
Table 3-3. RSTCTL_HARDRESET_STAT Register Description
Type Reset Description
R 0h Reserved. Always reads 0h
R 0h If 1, indicates that SRC15 was the source of the Hard Reset
R 0h If 1, indicates that SRC14 was the source of the Hard Reset
R 0h If 1, indicates that SRC13 was the source of the Hard Reset
R 0h If 1, indicates that SRC12 was the source of the Hard Reset
R 0h If 1, indicates that SRC11 was the source of the Hard Reset
R 0h If 1, indicates that SRC10 was the source of the Hard Reset
R 0h If 1, indicates that SRC9 was the source of the Hard Reset
R 0h If 1, indicates that SRC8 was the source of the Hard Reset
R 0h If 1, indicates that SRC7 was the source of the Hard Reset
R 0h If 1, indicates that SRC6 was the source of the Hard Reset
R 0h If 1, indicates that SRC5 was the source of the Hard Reset
R 0h If 1, indicates that SRC4 was the source of the Hard Reset
R 0h If 1, indicates that SRC3 was the source of the Hard Reset
R 0h If 1, indicates that SRC2 was the source of the Hard Reset
R 0h If 1, indicates that SRC1 was the source of the Hard Reset
R 0h If 1, indicates that SRC0 was the source of the Hard Reset
Copyright © 2015–2019, Texas Instruments Incorporated
23 22 21
Reserved
r r r r
8 7 6 5
SRC7 SRC6 SRC5
r-(0) r-(0) r-(0)
SLAU356I – March 2015 – Revised June 2019
www.ti.com
20 19 18 17
r r r r
4 3 2 1
SRC4 SRC3 SRC2 SRC1
r-(0) r-(0) r-(0) r-(0)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
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16
r
0
SRC0
r-(0)