Texas Instruments SimpleLink MSP432P4 Series Manuals

Texas Instruments SimpleLink MSP432P4 Series Manuals

Manuals and User Guides for Texas Instruments SimpleLink MSP432P4 Series. We have 1 Texas Instruments SimpleLink MSP432P4 Series manual available for free PDF download: Technical Reference Manual

Texas Instruments SimpleLink MSP432P4 Series Technical Reference Manual

Texas Instruments SimpleLink MSP432P4 Series Technical Reference Manual (1053 pages)

Brand: Texas Instruments | Category: Microcontrollers | Size: 7.04 MB

Table of Contents

Msp432P4Xx Simplelink™ Microcontrollers Technical Reference Manual

2
- Table of Contents
  2
16
- Preface
  
  48
- 1 Cortex-M4F Processor
  
  49
  - Introduction
    50
  - Cortex-M4F Optional Parameters Configuration in Msp432P4Xx
    51
    
    1.1.1 Block Diagram
    52
  - Overview
    53
    
    1.2.1 Bus Interface
    53
  - CPU Block Diagram
    53
  - Cortex-M4F Bus Interfaces in Msp432P4Xx
    53
    
    1.2.2 Integrated Configurable Debug
    54
    
    1.2.3 Cortex-M4F System Component Details
    54
  - Programming Model
    55
    
    1.3.1 Processor Mode and Privilege Levels for Software Execution
    55
    
    1.3.2 Stacks
    55
  - Summary of Processor Mode, Privilege Level, and Stack Use
    55
    
    1.3.3 Register Map
    56
    
    1.3.4 Register Descriptions
    56
  - Cortex-M4F Register Set
    56
  - PSR Register Combinations
    58
    
    1.3.5 Exceptions and Interrupts
    59
    
    1.3.6 Data Types
    59
  - Memory Model
    59
    
    1.4.1 Memory Regions, Types, and Attributes
    60
    
    1.4.2 Memory System Ordering of Memory Accesses
    61
    
    1.4.3 Behavior of Memory Accesses
    61
    
    1.4.4 Software Ordering of Memory Accesses
    61
  - Memory Access Behavior
    61
    
    1.4.5 Bit-Banding
    62
  - SRAM Memory Bit-Banding Regions
    63
  - Peripheral Memory Bit-Banding Regions
    63
    
    1.4.6 Data Storage
    64
  - Bit-Band Mapping
    64
  - Exception Model
    65
  - Data Storage
    65
    
    1.5.1 Exception States
    66
    
    1.5.2 Exception Types
    66
    
    1.5.3 Exception Handlers
    67
  - Exception Types
    67
  - Faults
    67
    
    1.5.4 Vector Table
    68
    
    1.5.5 Exception Priorities
    69
    
    1.5.6 Interrupt Priority Grouping
    69
    
    1.5.7 Level and Pulse Interrupts
    69
    
    1.5.8 Exception Entry and Return
    70
  - Exception Stack Frame
    71
  - Fault Handling
    72
  - Exception Return Behavior
    72
    
    1.6.1 Fault Types
    73
    
    1.6.2 Fault Escalation and Hard Faults
    73
    
    1.6.3 Fault Status Registers and Fault Address Registers
    74
    
    1.6.4 Lockup
    74
  - Power Management
    74
  - Fault Status and Fault Address Registers
    74
  - Instruction Set Summary
    75
  - Cortex-M4F Instruction Summary
    75
- 2 Cortex-M4F Peripherals
  
  80
  - Cortex-M4F Peripherals Introduction
    81
  - Functional Peripherals Description
    81
    
    System Timer (Systick)
    81
  - Core Peripheral Register Regions
    81
    
    Nested Vectored Interrupt Controller (NVIC)
    82
    
    System Control Block (SCB)
    83
    
    Memory Protection Unit (MPU)
    84
  - TEX, S, C, and B Bit Field Encoding
    85
  - Cache Policy for Memory Attribute Encoding
    85
  - AP Bit Field Encoding
    85
  - Memory Region Attributes for Msp432P4Xx Devices
    86
  - SRD Use Example
    88
  - FPU Register Bank
    89
  - Qnan and Snan Handling
    90
  - TPIU Block Diagram
    92
  - 2.4.1 FPU Registers
    93
  - FPCCR Register
    94
  - FPCCR Register Field Descriptions
    94
  - FPCAR Register
    95
  - FPCAR Register Field Descriptions
    95
  - FPDSCR Register
    96
  - MVFR0 Register
    97
  - MVFR0 Register Field Descriptions
    97
  - MVFR1 Register
    98
  - MVFR1 Register Field Descriptions
    98
  - 2.4.2 MPU Registers
    99
  - TYPE Register
    100
  - TYPE Register Field Descriptions
    100
  - CTRL Register
    101
  - CTRL Register Field Descriptions
    101
  - RNR Register
    102
  - RNR Register Field Descriptions
    102
  - RBAR Register
    103
  - RBAR Register Field Descriptions
    103
  - RASR Register
    104
  - RASR Register Field Descriptions
    104
  - RBAR_A1 Register
    106
  - RBAR_A1 Register Field Descriptions
    106
  - RASR_A1 Register
    107
  - RASR_A1 Register Field Descriptions
    108
  - RBAR_A2 Register
    109
  - RBAR_A2 Register Field Descriptions
    109
  - RASR_A2 Register
    110
  - RASR_A2 Register Field Descriptions
    111
  - RBAR_A3 Register
    112
  - RASR_A3 Register
    113
  - RASR_A3 Register Field Descriptions
    114
  - 2.4.3 NVIC Registers
    115
  - ISER0 Register
    116
  - ISER1 Register
    116
  - ISER0 Register Field Descriptions
    116
  - ISER1 Register Field Descriptions
    116
  - ICER0 Register
    117
  - ICER1 Register
    117
  - ICER0 Register Field Descriptions
    117
  - ICER1 Register Field Descriptions
    117
  - ISPR0 Register
    118
  - ISPR1 Register
    118
  - ISPR0 Register Field Descriptions
    118
  - ISPR1 Register Field Descriptions
    118
  - ICPR0 Register
    119
  - ICPR1 Register
    119
  - ICPR0 Register Field Descriptions
    119
  - ICPR1 Register Field Descriptions
    119
  - IABR0 Register
    120
  - IABR1 Register
    120
  - IABR0 Register Field Descriptions
    120
  - IABR1 Register Field Descriptions
    120
  - IPR0 Register
    121
  - IPR1 Register
    121
  - IPR0 Register Field Descriptions
    121
  - IPR1 Register Field Descriptions
    121
  - IPR2 Register
    122
  - IPR3 Register
    122
  - IPR2 Register Field Descriptions
    122
  - IPR3 Register Field Descriptions
    122
  - IPR4 Register
    123
  - IPR5 Register
    123
  - IPR4 Register Field Descriptions
    123
  - IPR5 Register Field Descriptions
    123
  - IPR6 Register
    124
  - IPR7 Register
    124
  - IPR6 Register Field Descriptions
    124
  - IPR7 Register Field Descriptions
    124
  - IPR8 Register
    125
  - IPR9 Register
    125
  - IPR8 Register Field Descriptions
    125
  - IPR9 Register Field Descriptions
    125
  - IPR10 Register
    126
  - IPR11 Register
    126
  - IPR10 Register Field Descriptions
    126
  - IPR11 Register Field Descriptions
    126
  - IPR12 Register
    127
  - IPR13 Register
    127
  - IPR12 Register Field Descriptions
    127
  - IPR13 Register Field Descriptions
    127
  - IPR14 Register
    128
  - IPR15 Register
    128
  - IPR14 Register Field Descriptions
    128
  - IPR15 Register Field Descriptions
    128
  - STIR Register
    129
  - STIR Register Field Descriptions
    129
  - 2.4.4 SYSTICK Registers
    130
  - STCSR Register
    131
  - STCSR Register Field Descriptions
    131
  - STRVR Register
    132
  - STRVR Register Field Descriptions
    132
  - STCVR Register
    133
  - STCVR Register Field Descriptions
    133
  - STCR Register
    134
  - STCR Register Field Descriptions
    134
    
    Bus
    135
  - 2.4.5 SCB Registers
    135
  - CPUID Register
    136
  - CPUID Register Field Descriptions
    136
  - ICSR Register
    137
  - ICSR Register Field Descriptions
    137
  - VTOR Register
    139
  - VTOR Register Field Descriptions
    139
  - AIRCR Register
    140
  - AIRCR Register Field Descriptions
    140
  - SCR Register
    142
  - SCR Register Field Descriptions
    142
  - CCR Register
    143
  - CCR Register Field Descriptions
    143
  - SHPR1 Register
    144
  - SHPR1 Register Field Descriptions
    144
  - SHPR2 Register
    145
  - SHPR2 Register Field Descriptions
    145
  - SHPR3 Register
    146
  - SHPR3 Register Field Descriptions
    146
  - SHCSR Register
    147
  - SHCSR Register Field Descriptions
    147
  - CFSR Register
    149
  - CFSR Register Field Descriptions
    149
  - HFSR Register
    151
  - HFSR Register Field Descriptions
    151
  - DFSR Register
    152
  - DFSR Register Field Descriptions
    152
  - MMFAR Register
    153
  - MMFAR Register Field Descriptions
    153
  - BFAR Register
    154
  - BFAR Register Field Descriptions
    154
  - AFSR Register
    155
  - AFSR Register Field Descriptions
    155
  - PFR0 Register
    156
  - PFR0 Register Field Descriptions
    156
  - PFR1 Register
    157
  - PFR1 Register Field Descriptions
    157
  - DFR0 Register
    158
  - DFR0 Register Field Descriptions
    158
  - AFR0 Register
    159
  - AFR0 Register Field Descriptions
    159
  - MMFR0 Register
    160
  - MMFR0 Register Field Descriptions
    160
  - MMFR1 Register
    161
  - MMFR1 Register Field Descriptions
    161
  - MMFR2 Register
    162
  - MMFR2 Register Field Descriptions
    162
  - MMFR3 Register
    163
  - MMFR3 Register Field Descriptions
    163
  - ISAR0 Register
    164
  - ISAR0 Register Field Descriptions
    164
  - ISAR1 Register
    165
  - ISAR1 Register Field Descriptions
    165
  - ISAR2 Register
    166
  - ISAR2 Register Field Descriptions
    166
  - ISAR3 Register
    167
  - ISAR3 Register Field Descriptions
    167
  - ISAR4 Register
    168
  - ISAR4 Register Field Descriptions
    168
  - CPACR Register
    169
  - 2.4.6 Scnscb Registers
    170
  - ICTR Register
    171
  - ICTR Register Field Descriptions
    171
  - ACTLR Register
    172
  - ACTLR Register Field Descriptions
    172
  - COREDEBUG Registers
    173
  - DHCSR Register
    174
  - DHCSR Register Field Descriptions
    174
  - DCRSR Register
    176
  - DCRSR Register Field Descriptions
    176
  - DCRDR Register
    177
  - DCRDR Register Field Descriptions
    177
  - DEMCR Register
    178
  - DEMCR Register Field Descriptions
    178
  - 2.5.1 FPB Registers
    180
  - FP_CTRL Register
    181
  - FP_CTRL Register Field Descriptions
    181
  - FP_REMAP Register
    182
  - FP_REMAP Register Field Descriptions
    182
  - FP_COMP0 Register
    183
  - FP_COMP0 Register Field Descriptions
    183
  - FP_COMP1 Register
    184
  - FP_COMP1 Register Field Descriptions
    184
  - FP_COMP2 Register
    185
  - FP_COMP2 Register Field Descriptions
    185
  - FP_COMP3 Register
    186
  - FP_COMP3 Register Field Descriptions
    186
  - FP_COMP4 Register
    187
  - FP_COMP4 Register Field Descriptions
    187
  - FP_COMP5 Register
    188
  - FP_COMP5 Register Field Descriptions
    188
  - FP_COMP6 Register
    189
  - FP_COMP6 Register Field Descriptions
    189
  - FP_COMP7 Register
    190
  - FP_COMP7 Register Field Descriptions
    190
  - CYCCNT Register
    191
  - 2.5.2 DWT Registers
    191
  - CTRL Register
    192
  - CTRL Register Field Descriptions
    192
  - CYCCNT Register Field Descriptions
    194
  - CPICNT Register
    195
  - CPICNT Register Field Descriptions
    195
  - EXCCNT Register
    196
  - EXCCNT Register Field Descriptions
    196
  - SLEEPCNT Register
    197
  - SLEEPCNT Register Field Descriptions
    197
  - LSUCNT Register
    198
  - LSUCNT Register Field Descriptions
    198
  - FOLDCNT Register
    199
  - FOLDCNT Register Field Descriptions
    199
  - PCSR Register
    200
  - PCSR Register Field Descriptions
    200
  - COMP0 Register
    201
  - COMP0 Register Field Descriptions
    201
  - MASK0 Register
    202
  - MASK0 Register Field Descriptions
    202
  - FUNCTION0 Register
    203
  - FUNCTION0 Register Field Descriptions
    203
  - COMP1 Register
    205
  - COMP1 Register Field Descriptions
    205
  - MASK1 Register
    206
  - MASK1 Register Field Descriptions
    206
  - FUNCTION1 Register
    207
  - FUNCTION1 Register Field Descriptions
    207
  - COMP2 Register
    209
  - COMP2 Register Field Descriptions
    209
  - MASK2 Register
    210
  - MASK2 Register Field Descriptions
    210
  - FUNCTION2 Register
    211
  - FUNCTION2 Register Field Descriptions
    211
  - COMP3 Register
    213
  - COMP3 Register Field Descriptions
    213
  - MASK3 Register
    214
  - MASK3 Register Field Descriptions
    214
  - FUNCTION3 Register
    215
  - FUNCTION3 Register Field Descriptions
    215
  - 2.5.3 ITM Registers
    217
  - STIM0 Register
    218
  - STIM0 Register Field Descriptions
    218
  - STIM1 Register
    219
  - STIM1 Register Field Descriptions
    219
  - STIM2 Register
    220
  - STIM2 Register Field Descriptions
    220
  - STIM3 Register
    221
  - STIM3 Register Field Descriptions
    221
  - STIM4 Register
    222
  - STIM4 Register Field Descriptions
    222
  - STIM5 Register
    223
  - STIM5 Register Field Descriptions
    223
  - STIM6 Register
    224
  - STIM6 Register Field Descriptions
    224
  - STIM7 Register
    225
  - STIM7 Register Field Descriptions
    225
  - STIM8 Register
    226
  - STIM8 Register Field Descriptions
    226
  - STIM9 Register
    227
  - STIM9 Register Field Descriptions
    227
  - STIM10 Register
    228
  - STIM10 Register Field Descriptions
    228
  - STIM11 Register
    229
  - STIM11 Register Field Descriptions
    229
  - STIM12 Register
    230
  - STIM12 Register Field Descriptions
    230
  - STIM13 Register
    231
  - STIM13 Register Field Descriptions
    231
  - STIM14 Register
    232
  - STIM14 Register Field Descriptions
    232
  - STIM15 Register
    233
  - STIM15 Register Field Descriptions
    233
  - STIM16 Register
    234
  - STIM16 Register Field Descriptions
    234
  - STIM17 Register
    235
  - STIM17 Register Field Descriptions
    235
  - STIM18 Register
    236
  - STIM18 Register Field Descriptions
    236
  - STIM19 Register
    237
  - STIM19 Register Field Descriptions
    237
  - STIM20 Register
    238
  - STIM20 Register Field Descriptions
    238
  - STIM21 Register
    239
  - STIM21 Register Field Descriptions
    239
  - STIM22 Register
    240
  - STIM22 Register Field Descriptions
    240
  - STIM23 Register
    241
  - STIM23 Register Field Descriptions
    241
  - STIM24 Register
    242
  - STIM24 Register Field Descriptions
    242
  - STIM25 Register
    243
  - STIM25 Register Field Descriptions
    243
  - STIM26 Register
    244
  - STIM26 Register Field Descriptions
    244
  - STIM27 Register
    245
  - STIM27 Register Field Descriptions
    245
  - STIM28 Register
    246
  - STIM28 Register Field Descriptions
    246
  - STIM29 Register
    247
  - STIM29 Register Field Descriptions
    247
  - STIM30 Register
    248
  - STIM30 Register Field Descriptions
    248
  - STIM31 Register
    249
  - STIM31 Register Field Descriptions
    249
  - TER Register
    250
  - TPR Register
    250
  - TER Register Field Descriptions
    250
  - TPR Register Field Descriptions
    250
  - TCR Register
    251
  - TCR Register Field Descriptions
    251
  - IWR Register
    252
  - IMCR Register
    252
  - IWR Register Field Descriptions
    252
  - IMCR Register Field Descriptions
    252
  - LAR Register
    253
  - LSR Register
    253
  - LAR Register Field Descriptions
    253
  - LSR Register Field Descriptions
    253
  - Reset Classes
    255
  - RSTCTL Registers
    258
  - RSTCTL_RESET_REQ Register
    259
  - RSTCTL_HARDRESET_STAT Register
    260
  - RSTCTL_HARDRESET_STAT Register Description
    260
  - RSTCTL_HARDRESET_CLR Register
    261
  - RSTCTL_HARDRESET_CLR Register Description
    261
  - RSTCTL_HARDRESET_SET Register
    262
  - RSTCTL_HARDRESET_SET Register Description
    262
  - RSTCTL_SOFTRESET_STAT Register
    263
  - RSTCTL_SOFTRESET_STAT Register Description
    263
  - RSTCTL_SOFTRESET_CLR Register
    264
  - RSTCTL_SOFTRESET_CLR Register Description
    264
  - RSTCTL_SOFTRESET_SET Register
    265
  - RSTCTL_SOFTRESET_SET Register Description
    265
  - RSTCTL_PSSRESET_STAT Register
    266
  - RSTCTL_PSSRESET_CLR Register
    266
  - RSTCTL_PSSRESET_STAT Register Description
    266
  - RSTCTL_PCMRESET_STAT Register
    267
  - RSTCTL_PCMRESET_CLR Register
    267
  - RSTCTL_PCMRESET_STAT Register Description
    267
  - RSTCTL_PINRESET_STAT Register
    268
  - RSTCTL_PINRESET_CLR Register
    268
  - RSTCTL_PINRESET_STAT Register Description
    268
  - RSTCTL_REBOOTRESET_STAT Register
    269
  - RSTCTL_REBOOTRESET_CLR Register
    269
  - RSTCTL_REBOOTRESET_STAT Register Description
    269
  - RSTCTL_REBOOTRESET_CLR Register Description
    269
  - RSTCTL_CSRESET_STAT Register
    270
  - RSTCTL_CSRESET_CLR Register
    270
  - RSTCTL_CSRESET_STAT Register Description
    270
System Controller (Sysctl)

271
- Device Memory Configuration and Status
  272
- SYSCTL Introduction
  272
- Glitch Filtering on Digital I/Os
  273
- NMI Configuration
  273
- Peripheral Halt Control
  273
- Watchdog Timer Reset Configuration
  273
- Device Security
  274
  - IP Protected Secure Zones Representation
    275
  - Data Setup for Encrypted Update
    277
  - Data Setup for IP Protected Secure Zone Unencrypted Update
    278
  - Boot Override Flow
    279
  - Factory Reset Boot Override Command through JTAG
    280
  - Boot Override Flash Mailbox
    281
  - Boot Override Flash Mailbox
    282
  - Acks Used by Boot-Code to Indicate Status of Boot Override
    286
  - Commands Used by Boot-Code for Boot Override
    286
  - Device Descriptor Table
    289
  - Tag Values
    290
  - Clock System Calibration Data
    291
  - ADC Calibration Data
    292
  - BSL Configuration Data
    293
  - Flash Information Descriptor
    293
  - Random Number Seed
    293
  - 4.10 Arm Cortex-M4F ROM Table Based Part Number
    294
  - Arm Cortex-M4 Peripheral ID Register Description
    294
  - Example of ROM PID Entries for Msp432P401Xx MCU
    294
  - Structure of Device Identification Code
    294
  - 4.11 SYSCTL Registers
    295
  - SYS_REBOOT_CTL Register Description
    296
  - SYS_NMI_CTLSTAT Register
    297
  - SYS_NMI_CTLSTAT Register Description
    297
  - SYS_WDTRESET_CTL Register
    298
  - SYS_PERIHALT_CTL Register
    299
  - SYS_PERIHALT_CTL Register Description
    299
  - SYS_SRAM_SIZE Register Description
    300
  - SYS_SRAM_BANKEN Register
    301
  - SYS_SRAM_BANKEN Register Description
    301
  - SYS_SRAM_BANKRET Register
    302
  - SYS_SRAM_BANKRET Register Description
    302
  - SYS_FLASH_SIZE Register
    303
  - SYS_DIO_GLTFLT_CTL Register Description
    304
  - SYS_SECDATA_UNLOCK Register Description
    305
  - SYS_MASTER_UNLOCK Register
    306
  - SYS_MASTER_UNLOCK Register Description
    306
  - SYS_BOOTOVER_REQ0 Register
    307
  - SYS_BOOTOVER_REQ0 Register Description
    307
  - SYS_BOOTOVER_REQ1 Register
    308
  - SYS_BOOTOVER_REQ1 Register Description
    308
  - SYS_BOOTOVER_ACK Register Description
    309
  - SYS_RESET_REQ Register Description
    310
  - SYS_RESET_STATOVER Register
    311
  - SYS_RESET_STATOVER Register Description
    311
  - SYS_SYSTEM_STAT Register
    312
  - SYS_SYSTEM_STAT Register Description
    312
  - Example Bank and Block Organization of SRAM
    314
  - IP Protected Secure Zones Representation
    317
  - Data Setup for Encrypted Update
    320
  - Data Setup for IP Protected Secure Zone Unencrypted Update
    320
  - Boot Override Flow
    322
  - Factory Reset Boot Override Command through JTAG
    323
  - Boot Override Parameters Restrictions
    329
  - Commands Used by Boot-Code for Boot Override
    329
  - Acks Used by Boot-Code to Indicate Status of Boot Override
    330
  - Device Descriptor Table
    332
  - Tag Values
    333
  - Clock System Calibration Data
    334
  - ADC Calibration Data
    335
  - BSL Configuration Data
    336
  - Flash Information Descriptor
    336
  - Random Number Seed
    336
  - Arm Cortex-M4 Peripheral ID Register Description
    337
  - Example of ROM PID Entries for Msp432P401Xx MCU
    337
  - Structure of Device Identification Code
    337
  - SYS_REBOOT_CTL Register
    339
  - SYS_NMI_CTLSTAT Register
    340
  - SYS_NMI_CTLSTAT Register Description
    340
  - SYS_WDTRESET_CTL Register
    341
  - SYS_WDTRESET_CTL Register Description
    341
  - SYS_PERIHALT_CTL Register
    342
  - SYS_PERIHALT_CTL Register Description
    342
  - SYS_SRAM_SIZE Register
    343
  - SYS_SRAM_NUMBANKS Register
    344
  - SYS_SRAM_NUMBANKS Register Description
    344
  - SYS_SRAM_NUMBLOCKS Register
    345
  - SYS_SRAM_NUMBLOCKS Register Description
    345
  - SYS_MAINFLASH_SIZE Register
    346
  - SYS_MAINFLASH_SIZE Register Description
    346
  - SYS_INFOFLASH_SIZE Register
    347
  - SYS_INFOFLASH_SIZE Register Description
    347
  - SYS_DIO_GLTFLT_CTL Register
    348
  - Sys_Secdata_Unlock
    349
  - SYS_SRAM_BANKEN_CTL0 Register Description
    350
  - SYS_SRAM_BANKEN_CTL0 Register
    352
  - SYS_SRAM_BANKEN_CTL1 Register
    353
  - SYS_SRAM_BANKEN_CTL1 Register Description
    353
  - SYS_SRAM_BANKEN_CTL2 Register
    356
  - SYS_SRAM_BANKEN_CTL2 Register Description
    356
  - SYS_SRAM_BANKEN_CTL3 Register
    359
  - SYS_SRAM_BANKEN_CTL3 Register Description
    359
  - SYS_SRAM_BLKRET_CTL0 Register
    362
  - SYS_SRAM_BLKRET_CTL0 Register Description
    362
  - SYS_SRAM_BLKRET_CTL1 Register
    364
  - SYS_SRAM_BLKRET_CTL1 Register Description
    364
  - SYS_SRAM_BLKRET_CTL2 Register
    366
  - SYS_SRAM_BLKRET_CTL2 Register Description
    366
  - SYS_SRAM_BLKRET_CTL3 Register
    368
  - SYS_SRAM_BLKRET_CTL3 Register Description
    368
  - SYS_SRAM_STAT Register
    370
  - SYS_MASTER_UNLOCK Register
    371
  - SYS_MASTER_UNLOCK Register Description
    371
  - SYS_BOOTOVER_REQ0 Register
    372
  - SYS_BOOTOVER_REQ0 Register Description
    372
  - SYS_BOOTOVER_REQ1 Register
    373
  - SYS_BOOTOVER_REQ1 Register Description
    373
  - SYS_BOOTOVER_ACK Register
    374
  - SYS_RESET_REQ Register
    375
  - SYS_RESET_STATOVER Register
    376
  - SYS_RESET_STATOVER Register Description
    376
  - SYS_SYSTEM_STAT Register
    377
  - Clock System Block Diagram
    380
  - HFXTFREQ Settings
    382
  - Module Clock Request System
    388
  - Oscillator Fault Logic
    390
  - Switch MCLK from DCOCLK to LFXTCLK
    392
  - CS Registers
    393
  - CSKEY Register
    394
  - CSKEY Register Description
    394
  - CSCTL0 Register
    395
  - CSCTL0 Register Description
    395
  - CSCTL1 Register
    396
  - CSCTL1 Register Description
    396
  - CSCTL2 Register
    398
  - CSCTL2 Register Description
    398
  - CSCTL3 Register
    400
  - CSCTL3 Register Description
    400
  - CSCLKEN Register
    401
  - CSCLKEN Register Description
    401
  - CSSTAT Register
    402
  - CSSTAT Register Description
    402
  - CSIE Register
    404
  - CSIE Register Description
    404
  - CSIFG Register
    405
  - CSIFG Register Description
    405
  - CSCLRIFG Register
    406
  - CSCLRIFG Register Description
    406
  - CSSETIFG Register
    407
  - CSSETIFG Register Description
    407
  - CSDCOERCAL0 Register
    408
  - CSDCOERCAL1 Register
    409
  - CSDCOERCAL1 Register Description
    409
  - PSS Block Diagram
    411
  - PSS Action at Device Power-Up
    413
  - Supply Voltage Failure and Resulting PSS Action
    413
  - PSS Registers
    415
  - PSSKEY Register
    416
  - PSSKEY Register Description
    416
  - PSSCTL0 Register
    417
  - PSSCTL0 Register Description
    417
  - PSSIE Register
    419
  - PSSIE Register Description
    419
  - PSSIFG Register
    420
  - PSSIFG Register Description
    420
  - PSSCLRIFG Register
    421
  - PSSCLRIFG Register Description
    421
  - Power Control Manager Interaction
    423
  - Power Modes Summary for MSP432P401R and MSP432P401M Devices
    427
  - Power Modes Summary for All Msp432P4Xx Devices Except MSP432P401R and MSP432P401M
    429
  - High-Level Power-Mode Transitions
    431
  - Valid Active Mode Transitions
    432
  - Valid LPM0 Transitions
    432
  - Valid LPM3 and LPM4 Transitions
    433
  - Valid LPM3.5 and LPM4.5 Transitions
    434
  - Power Mode Selection
    436
  - AM Invalid Transition Nmi/Interrupt Enable
    437
  - LPM Invalid Transition Nmi/Interrupt Enable
    437
  - PCM Static Clock Request Checks
    437
  - LPM Clock Checks Nmi/Interrupt Enable
    438
  - Active Mode Transition Flow
    439
  - DC/DC Error Nmi/Interrupt Enable
    439
  - SVSMH Performance and Power Modes
    443
  - Wake-Up Sources from Low-Power Modes for MSP432P401R and MSP432P401M Devices
    445
  - Wake-Up Sources from Low-Power Modes for All Msp432P4Xx Devices Except MSP432P401R and MSP432P401M
    446
  - 8.26 PCM Registers
    448
  - PCMCTL0 Register
    449
  - PCMCTL0 Register Description
    449
  - PCMCTL1 Register
    451
  - PCMCTL1 Register Description
    451
  - PCMIE Register
    453
  - PCMIE Register Description
    453
  - PCMIFG Register
    454
  - PCMIFG Register Description
    454
  - PCMCLRIFG Register
    455
  - PCMCLRIFG Register Description
    455
  - MSP432 Driver Library API for Flash Wait-State Configuration
    458
  - MSP432 Driver Library API for Flash Program Operation
    459
  - MSP432 Driver Library API for Flash Read Buffering Configuration
    459
  - MSP432 Driver Library API for Flash Sector Erase Operation
    459
  - MSP432 Driver Library API for Flash Mass Erase Operation
    460
  - MSP432 Driver Library API for Setting up Program or Erase Operation
    460
  - MSP432 Driver Library API for Setting up Flash Read Modes
    461
  - Configuring the Auto-Verify Mode through Direct Register Access
    462
  - MSP432 Driver Library API for Setting up Auto-Verify before Program Operations
    462
  - MSP432 Driver Library API for Enabling Program Operations
    463
  - Immediate and Full Word Program Flow
    464
  - Pre-Verify Error Handling for Immediate and Full Word Program Flow
    465
  - Post-Verify Error Handling for Immediate and Full Word Program Flow
    466
  - Burst Program Flow
    468
  - Handling Auto-Verify Error before the Burst Operation
    469
  - Handling Auto-Verify Error after the Burst Operation
    470
  - MSP432 Driver Library API for Flash Erase Operations
    471
  - FLCTL Registers
    475
  - FLCTL_POWER_STAT Register
    477
  - FLCTL_POWER_STAT Register Description
    477
  - FLCTL_BANK0_RDCTL Register
    478
  - FLCTL_BANK0_RDCTL Register Description
    478
  - FLCTL_BANK0_RDCTL Register Description
    479
  - FLCTL_BANK1_RDCTL Register
    480
  - FLCTL_BANK1_RDCTL Register Description
    480
  - FLCTL_BANK1_RDCTL Register Description
    481
  - FLCTL_RDBRST_CTLSTAT Register
    482
  - FLCTL_RDBRST_CTLSTAT Register Description
    482
  - FLCTL_RDBRST_STARTADDR Register
    483
  - FLCTL_RDBRST_STARTADDR Register Description
    483
  - FLCTL_RDBRST_LEN Register Description
    484
  - FLCTL_RDBRST_FAILADDR Register
    485
  - FLCTL_RDBRST_FAILADDR Register Description
    485
  - FLCTL_RDBRST_FAILCNT Register
    486
  - FLCTL_RDBRST_FAILCNT Register Description
    486
  - FLCTL_PRG_CTLSTAT Register
    487
  - FLCTL_PRG_CTLSTAT Register Description
    487
  - FLCTL_PRGBRST_CTLSTAT Register
    488
  - FLCTL_PRGBRST_CTLSTAT Register Description
    488
  - FLCTL_PRGBRST_CTLSTAT Register Description
    489
  - FLCTL_PRGBRST_STARTADDR Register
    489
  - FLCTL_PRGBRST_STARTADDR Register
    490
  - FLCTL_PRGBRST_STARTADDR Register Description
    490
  - FLCTL_PRGBRST_DATA0_0 Register Description
    491
  - FLCTL_PRGBRST_DATA0_1 Register Description
    491
  - FLCTL_PRGBRST_DATA0_2 Register Description
    492
  - FLCTL_PRGBRST_DATA0_3 Register Description
    492
  - FLCTL_PRGBRST_DATA1_0 Register Description
    493
  - FLCTL_PRGBRST_DATA1_1 Register Description
    493
  - FLCTL_PRGBRST_DATA1_2 Register Description
    494
  - FLCTL_PRGBRST_DATA1_3 Register Description
    494
  - FLCTL_PRGBRST_DATA2_0 Register Description
    495
  - FLCTL_PRGBRST_DATA2_1 Register Description
    495
  - FLCTL_PRGBRST_DATA2_2 Register Description
    496
  - FLCTL_PRGBRST_DATA2_3 Register Description
    496
  - FLCTL_PRGBRST_DATA3_0 Register Description
    497
  - FLCTL_PRGBRST_DATA3_1 Register Description
    497
  - FLCTL_PRGBRST_DATA3_2 Register Description
    498
  - FLCTL_PRGBRST_DATA3_3 Register Description
    498
  - FLCTL_ERASE_CTLSTAT Register
    499
  - FLCTL_ERASE_CTLSTAT Register Description
    499
  - FLCTL_ERASE_SECTADDR Register
    500
  - FLCTL_ERASE_SECTADDR Register Description
    500
  - FLCTL_BANK0_INFO_WEPROT Register
    501
  - FLCTL_BANK0_INFO_WEPROT Register Description
    501
  - FLCTL_BANK0_MAIN_WEPROT Register
    502
  - FLCTL_BANK0_MAIN_WEPROT Register Description
    502
  - FLCTL_BANK1_INFO_WEPROT Register
    504
  - FLCTL_BANK1_INFO_WEPROT Register Description
    504
  - FLCTL_BANK1_MAIN_WEPROT Register
    505
  - FLCTL_BANK1_MAIN_WEPROT Register Description
    505
  - FLCTL_BMRK_CTLSTAT Register
    507
  - FLCTL_BMRK_CTLSTAT Register Description
    507
  - FLCTL_BMRK_IFETCH Register
    508
  - FLCTL_BMRK_IFETCH Register Description
    508
  - FLCTL_BMRK_DREAD Register
    509
  - FLCTL_BMRK_DREAD Register Description
    509
  - FLCTL_BMRK_CMP Register Description
    510
  - FLCTL_IFG Register Description
    511
  - FLCTL_IE Register Description
    512
  - FLCTL_CLRIFG Register Description
    513
  - FLCTL_SETIFG Register Description
    514
  - FLCTL_READ_TIMCTL Register
    515
  - FLCTL_READ_TIMCTL Register Description
    515
  - FLCTL_READMARGIN_TIMCTL Register
    516
  - FLCTL_READMARGIN_TIMCTL Register Description
    516
  - FLCTL_PRGVER_TIMCTL Register
    517
  - FLCTL_PRGVER_TIMCTL Register Description
    517
  - FLCTL_ERSVER_TIMCTL Register
    518
  - FLCTL_ERSVER_TIMCTL Register Description
    518
  - FLCTL_PROGRAM_TIMCTL Register
    519
  - FLCTL_PROGRAM_TIMCTL Register Description
    519
  - FLCTL_ERASE_TIMCTL Register
    520
  - FLCTL_ERASE_TIMCTL Register Description
    520
  - FLCTL_MASSERASE_TIMCTL Register
    521
  - FLCTL_MASSERASE_TIMCTL Register Description
    521
  - FLCTL_BURSTPRG_TIMCTL Register
    522
  - FLCTL_BURSTPRG_TIMCTL Register Description
    522
  - MSP432 Driver Library API for FLCTL_A Wait-State Configuration
    525
  - MSP432 Driver Library API for FLCTL_A Program Operation
    526
  - MSP432 Driver Library API for FLCTL_A Read Buffering Configuration
    526
  - MSP432 Driver Library API for FLCTL_A Sector Erase Operation
    526
  - MSP432 Driver Library API for FLCTL_A Mass Erase Operation
    527
  - MSP432 Driver Library API for Setting up FLCTL_A Program or Erase Protection
    527
  - Configuring the Auto-Verify Mode through Direct Register Access
    529
  - MSP432 Driver Library API for Enabling FLCTL_A Program Operations
    530
  - Immediate and Full Word Program Flow
    531
  - Pre-Verify Error Handling for Immediate and Full Word Program Flow
    532
  - Post-Verify Error Handling for Immediate and Full Word Program Flow
    533
  - Burst Program Flow
    535
  - Handling Auto-Verify Error before the Burst Operation
    536
  - Handling Auto-Verify Error after the Burst Operation
    537
  - MSP432 Driver Library API for FLCTL_A Erase Operations
    538
  - FLCTL_A Registers
    543
  - FLCTL_POWER_STAT Register
    544
  - FLCTL_POWER_STAT Register Description
    544
  - FLCTL_BANK0_RDCTL Register
    545
  - FLCTL_BANK1_RDCTL Register
    547
  - FLCTL_RDBRST_CTLSTAT Register
    549
  - FLCTL_RDBRST_CTLSTAT Register Description
    549
  - FLCTL_RDBRST_STARTADDR Register
    550
  - FLCTL_RDBRST_STARTADDR Register Description
    550
  - FLCTL_RDBRST_LEN Register
    551
  - FLCTL_RDBRST_FAILADDR Register
    552
  - FLCTL_RDBRST_FAILADDR Register Description
    552
  - FLCTL_RDBRST_FAILCNT Register
    553
  - FLCTL_RDBRST_FAILCNT Register Description
    553
  - FLCTL_PRG_CTLSTAT Register
    554
  - FLCTL_PRG_CTLSTAT Register Description
    554
  - FLCTL_PRGBRST_CTLSTAT Register
    555
  - FLCTL_PRGBRST_STARTADDR Register Description
    557
  - FLCTL_PRGBRST_DATA0_0 Register
    558
  - FLCTL_PRGBRST_DATA0_1 Register
    558
  - FLCTL_PRGBRST_DATA0_2 Register
    559
  - FLCTL_PRGBRST_DATA0_3 Register
    559
  - FLCTL_PRGBRST_DATA1_0 Register
    560
  - FLCTL_PRGBRST_DATA1_1 Register
    560
  - FLCTL_PRGBRST_DATA1_2 Register
    561
  - FLCTL_PRGBRST_DATA1_3 Register
    561
  - FLCTL_PRGBRST_DATA2_0 Register
    562
  - FLCTL_PRGBRST_DATA2_1 Register
    562
  - FLCTL_PRGBRST_DATA2_2 Register
    563
  - FLCTL_PRGBRST_DATA2_3 Register
    563
  - FLCTL_PRGBRST_DATA3_0 Register
    564
  - FLCTL_PRGBRST_DATA3_1 Register
    564
  - FLCTL_PRGBRST_DATA3_2 Register
    565
  - FLCTL_PRGBRST_DATA3_3 Register
    565
  - FLCTL_ERASE_CTLSTAT Register
    566
  - FLCTL_ERASE_CTLSTAT Register Description
    566
  - FLCTL_ERASE_SECTADDR Register
    567
  - FLCTL_ERASE_SECTADDR Register Description
    567
  - FLCTL_BANK0_INFO_WEPROT Register
    568
  - FLCTL_BANK0_INFO_WEPROT Register Description
    568
  - FLCTL_BANK0_MAIN_WEPROT Register
    569
  - FLCTL_BANK0_MAIN_WEPROT Register Description
    569
  - FLCTL_BANK1_INFO_WEPROT Register
    571
  - FLCTL_BANK1_INFO_WEPROT Register Description
    571
  - FLCTL_BANK1_MAIN_WEPROT Register
    572
  - FLCTL_BANK1_MAIN_WEPROT Register Description
    572
  - FLCTL_BMRK_CTLSTAT Register
    574
  - FLCTL_BMRK_CTLSTAT Register Description
    574
  - FLCTL_BMRK_IFETCH Register
    575
  - FLCTL_BMRK_IFETCH Register Description
    575
  - FLCTL_BMRK_DREAD Register
    576
  - FLCTL_BMRK_DREAD Register Description
    576
  - FLCTL_BMRK_CMP Register
    577
  - FLCTL_IFG Register
    578
  - FLCTL_IE Register
    579
  - FLCTL_CLRIFG Register
    580
  - FLCTL_SETIFG Register
    581
  - FLCTL_READ_TIMCTL Register
    582
  - FLCTL_READ_TIMCTL Register Description
    582
  - FLCTL_READMARGIN_TIMCTL Register
    583
  - FLCTL_READMARGIN_TIMCTL Register Description
    583
  - FLCTL_PRGVER_TIMCTL Register
    584
  - FLCTL_PRGVER_TIMCTL Register Description
    584
  - FLCTL_ERSVER_TIMCTL Register
    585
  - FLCTL_ERSVER_TIMCTL Register Description
    585
  - FLCTL_PROGRAM_TIMCTL Register
    586
  - FLCTL_PROGRAM_TIMCTL Register Description
    586
  - FLCTL_ERASE_TIMCTL Register
    587
  - FLCTL_ERASE_TIMCTL Register Description
    587
  - FLCTL_MASSERASE_TIMCTL Register
    588
  - FLCTL_MASSERASE_TIMCTL Register Description
    588
  - FLCTL_BURSTPRG_TIMCTL Register
    589
  - FLCTL_BURSTPRG_TIMCTL Register Description
    589
  - FLCTL_BANK0_MAIN_WEPROT0 Register
    590
  - FLCTL_BANK0_MAIN_WEPROT0 Register Description
    590
  - FLCTL_BANK0_MAIN_WEPROT1 Register
    592
  - FLCTL_BANK0_MAIN_WEPROT1 Register Description
    592
  - FLCTL_BANK0_MAIN_WEPROT2 Register
    594
  - FLCTL_BANK0_MAIN_WEPROT2 Register Description
    594
  - FLCTL_BANK0_MAIN_WEPROT3 Register
    596
  - FLCTL_BANK0_MAIN_WEPROT3 Register Description
    596
  - FLCTL_BANK0_MAIN_WEPROT4 Register
    598
  - FLCTL_BANK0_MAIN_WEPROT4 Register Description
    598
  - FLCTL_BANK0_MAIN_WEPROT5 Register
    600
  - FLCTL_BANK0_MAIN_WEPROT5 Register Description
    600
  - FLCTL_BANK0_MAIN_WEPROT6 Register
    602
  - FLCTL_BANK0_MAIN_WEPROT6 Register Description
    602
  - FLCTL_BANK0_MAIN_WEPROT7 Register
    604
  - FLCTL_BANK0_MAIN_WEPROT7 Register Description
    604
  - FLCTL_BANK1_MAIN_WEPROT0 Register
    606
  - FLCTL_BANK1_MAIN_WEPROT0 Register Description
    606
  - FLCTL_BANK1_MAIN_WEPROT1 Register
    608
  - FLCTL_BANK1_MAIN_WEPROT1 Register Description
    608
  - FLCTL_BANK1_MAIN_WEPROT2 Register
    610
  - FLCTL_BANK1_MAIN_WEPROT2 Register Description
    610
  - FLCTL_BANK1_MAIN_WEPROT3 Register
    612
  - FLCTL_BANK1_MAIN_WEPROT3 Register Description
    612
  - FLCTL_BANK1_MAIN_WEPROT4 Register
    614
  - FLCTL_BANK1_MAIN_WEPROT4 Register Description
    614
  - FLCTL_BANK1_MAIN_WEPROT5 Register
    616
  - FLCTL_BANK1_MAIN_WEPROT5 Register Description
    616
  - FLCTL_BANK1_MAIN_WEPROT6 Register
    618
  - FLCTL_BANK1_MAIN_WEPROT6 Register Description
    618
  - FLCTL_BANK1_MAIN_WEPROT7 Register
    620
  - FLCTL_BANK1_MAIN_WEPROT7 Register Description
    620
  - DMA Block Diagram
    624
  - Address Increments
    625
  - Protection Signaling
    625
  - DMA Signaling When Peripherals Use Pulse Requests
    626
  - Key Handshake Rules for the DMA Controller
    626
  - DMA Signaling When Peripherals Use Level Requests
    627
  - AHB Bus Transfer Arbitration Interval
    628
  - DMA Channel Priority
    629
  - Polling Flowchart
    629
  - DMA Cycle Types
    630
  - Ping-Pong Example
    632
  - Channel_Cfg for a Primary Data Structure, in Memory Scatter-Gather Mode
    634
  - Memory Scatter-Gather Example
    635
  - Channel_Cfg for a Primary Data Structure, in Peripheral Scatter-Gather Mode
    637
  - Peripheral Scatter-Gather Example
    638
  - Memory Map for 32 Channels, Including the Alternate Data Structure
    640
  - Address Bit Settings for the Channel Control Data Structure
    641
  - Memory Map for Three DMA Channels, Including the Alternate Data Structure
    642
  - Permitted Base Addresses
    642
  - Channel_Cfg Bit Assignments
    643
  - Dst_Data_End_Ptr Bit Assignments
    643
  - Rc_Data_End_Ptr Bit Assignments
    643
  - Channel_Cfg Bit Assignments
    644
  - 11.3 DMA Registers
    648
  - DMA_DEVICE_CFG Register
    649
  - DMA_SW_CHTRIG Register
    650
  - DMA_SW_CHTRIG Register Description
    650
  - Dma_Chn_Srccfg Register
    652
  - Dma_Chn_Srccfg Register Description
    652
  - DMA_INT1_SRCCFG Register
    653
  - DMA_INT1_SRCCFG Register Description
    653
  - DMA_INT2_SRCCFG Register
    654
  - DMA_INT2_SRCCFG Register Description
    654
  - DMA_INT3_SRCCFG Register
    655
  - DMA_INT3_SRCCFG Register Description
    655
  - DMA_INT0_SRCFLG Register
    656
  - DMA_INT0_SRCFLG Register Description
    656
  - DMA_INT0_CLRFLG Register
    657
  - DMA_INT0_CLRFLG Register Description
    657
  - DMA_STAT Register
    659
  - DMA_STAT Register Field Descriptions
    659
  - DMA_CFG Register
    660
  - DMA_CFG Register Field Descriptions
    660
  - DMA_CTLBASE Register
    661
  - DMA_CTLBASE Register Field Descriptions
    661
  - DMA_ALTBASE Register
    662
  - DMA_ALTBASE Register Field Descriptions
    662
  - DMA_WAITSTAT Register
    663
  - DMA_WAITSTAT Register Field Descriptions
    663
  - DMA_SWREQ Register
    664
  - DMA_SWREQ Register Field Descriptions
    664
  - DMA_USEBURSTSET Register
    665
  - DMA_USEBURSTSET Register Field Descriptions
    665
  - DMA_USEBURSTCLR Register
    666
  - DMA_USEBURSTCLR Register Field Descriptions
    666
  - DMA_REQMASKSET Register
    667
  - DMA_REQMASKSET Register Field Descriptions
    667
  - DMA_REQMASKCLR Register
    668
  - DMA_REQMASKCLR Register Field Descriptions
    668
  - DMA_ENASET Register
    669
  - DMA_ENASET Register Field Descriptions
    669
  - DMA_ENACLR Register
    670
  - DMA_ENACLR Register Field Descriptions
    670
  - DMA_ALTSET Register
    671
  - DMA_ALTSET Register Field Descriptions
    671
  - DMA_ALTCLR Register
    672
  - DMA_ALTCLR Register Field Descriptions
    672
  - DMA_PRIOSET Register
    673
  - DMA_PRIOSET Register Field Descriptions
    673
  - DMA_PRIOCLR Register
    674
  - DMA_PRIOCLR Register Field Descriptions
    674
  - DMA_ERRCLR Register
    675
  - DMA_ERRCLR Register Field Descriptions
    675
  - I/O Function Selection
    679
  - 12.4 Digital I/O Registers
    683
  - Pxiv Register
    695
  - Pxiv Register Description
    695
  - Pxdir Register
    696
  - Pxdir Register Description
    696
  - Pxin Register
    696
  - Pxin Register Description
    696
  - Pxout Register
    696
  - Pxout Register Description
    696
  - Pxds Register
    697
  - Pxds Register Description
    697
  - Pxren Register
    697
  - Pxren Register Description
    697
  - Pxsel0 Register
    697
  - Pxsel0 Register Description
    697
  - P1IES Register Description
    698
  - Pxies Register
    698
  - Pxsel1 Register
    698
  - Pxsel1 Register Description
    698
  - Pxselc Register
    698
  - Pxselc Register Description
    698
  - Pxie Register
    699
  - Pxie Register Description
    699
  - Pxifg Register
    699
  - Pxifg Register Description
    699
  - Examples for Port Mapping Mnemonics and Functions
    702
  - 13.3 PMAP Registers
    704
  - P1MAP0 to P1MAP7 Register
    706
  - PMAPCTL Register
    706
  - PMAPCTL Register Description
    706
  - PMAPKEYID Register
    706
  - PMAPKEYID Register Description
    706
  - P2MAP0 to P2MAP7 Register
    707
  - P2MAP0 to P2MAP7 Register Description
    707
  - P3MAP0 to P3MAP7 Register
    707
  - P3MAP0 to P3MAP7 Register Description
    707
  - P4MAP0 to P4MAP7 Register
    707
  - P4MAP0 to P4MAP7 Register Description
    707
  - P5MAP0 to P5MAP7 Register
    707
  - P5MAP0 to P5MAP7 Register Description
    708
  - P6MAP0 to P6MAP7 Register
    708
  - P7MAP0 to P7MAP7 Register
    708
  - Pxmapyz Register
    708
  - Pxmapyz Register Description
    708
  - Capacitive Touch IO Principle
    710
  - Capacitive Touch IO Block Diagram
    711
  - 14.3 Captouch Registers
    712
  - Captioxctl Register
    713
  - Captioxctl Register Description
    713
  - LFSR Implementation of CRC-CCITT as Defined in Standard (Bit0 Is MSB)
    715
  - LFSR Implementation of CRC32-ISO3309 as Defined in Standard (Bit0 Is MSB)
    715
  - 15.3 CRC32 Registers
    717
  - CRC32DI Register
    718
  - CRC32DI Register Description
    718
  - CRC32DIRB Register
    719
  - CRC32DIRB Register Description
    719
  - CRC32INIRES_LO Register
    720
  - CRC32INIRES_HI Register
    721
  - CRC32RESR_LO Register
    722
  - CRC32RESR_HI Register
    723
  - CRC16DI Register
    724
  - CRC16DI Register Description
    724
  - CRC16DIRB Register
    725
  - CRC16DIRB Register Description
    725
  - CRC16INIRES Register
    726
  - CRC16INIRES Register Description
    726
  - CRC16RESR Register
    727
  - CRC16RESR Register Description
    727
  - AES Accelerator Block Diagram
    729
  - AES Operation Modes Overview
    730
  - AES State Array Input and Output
    730
  - AES Encryption Process for 128-Bit Key
    733
  - AES Decryption Process Using Aesopx = 01 for 128-Bit Key
    734
  - AES Decryption Process Using Aesopx = 10 and 11 for 128-Bit Key
    735
  - AES Trigger 0-2' Operation When AESCMEN = 1
    737
  - AES and DMA Configuration for ECB Encryption
    738
  - ECB Encryption
    738
  - AES DMA Configuration for ECB Decryption
    739
  - ECB Decryption
    739
  - AES and DMA Configuration for CBC Encryption
    740
  - CBC Encryption
    740
  - AES and DMA Configuration for CBC Decryption
    741
  - CBC Decryption
    741
  - AES and DMA Configuration for OFB Encryption
    742
  - OFB Encryption
    742
  - AES and DMA Configuration for OFB Decryption
    743
  - OFB Decryption
    743
  - AES and DMA Configuration for CFB Encryption
    744
  - CFB Encryption
    744
  - AES and DMA Configuration for CFB Decryption
    745
  - CFB Decryption
    745
  - 16.3 AES256 Registers
    746
  - AESACTL0 Register
    747
  - AESACTL0 Register Description
    747
  - AESACTL1 Register
    749
  - AESACTL1 Register Description
    749
  - AESASTAT Register
    750
  - AESASTAT Register Description
    750
  - AESAKEY Register
    751
  - AESAKEY Register Description
    751
  - AESADIN Register
    752
  - AESADIN Register Description
    752
  - AESADOUT Register
    753
  - AESADOUT Register Description
    753
  - AESAXDIN Register
    754
  - AESAXDIN Register Description
    754
  - AESAXIN Register
    755
  - AESAXIN Register Description
    755
  - WDT_A Registers
    756
  - Watchdog Timer Block Diagram
    758
  - WDT_A Clock Sources
    760
  - WDTCTL Register
    763
  - WDTCTL Register Description
    763
  - Prescale Clock Enable Generation
    766
  - 18.5 Timer32 Registers
    767
  - T32LOAD1 Register
    768
  - T32LOAD1 Register Description
    768
  - T32VALUE1 Register
    769
  - T32VALUE1 Register Description
    769
  - T32CONTROL1 Register
    770
  - T32CONTROL1 Register Description
    770
  - T32INTCLR1 Register
    771
  - T32INTCLR1 Register Description
    771
  - T32RIS1 Register
    772
  - T32MIS1 Register
    773
  - T32BGLOAD1 Register
    774
  - T32BGLOAD1 Register Description
    774
  - T32LOAD2 Register
    775
  - T32LOAD2 Register Description
    775
  - T32VALUE2 Register
    776
  - T32VALUE2 Register Description
    776
  - T32CONTROL2 Register
    777
  - T32CONTROL2 Register Description
    777
  - T32INTCLR2 Register
    778
  - T32INTCLR2 Register Description
    778
  - T32RIS2 Register
    779
  - T32MIS2 Register
    780
  - T32BGLOAD2 Register
    781
  - T32BGLOAD2 Register Description
    781
  - Timer_A Block Diagram
    784
  - Mode
    786
  - Timer Modes
    786
  - Up Mode
    786
  - Up Mode Flag Setting
    786
  - Continuous Mode
    787
  - Continuous Mode Flag Setting
    787
  - Continuous Mode Time Intervals
    787
  - Up/Down Mode
    788
  - Up/Down Mode Flag Setting
    788
  - Output Unit in Up/Down Mode
    789
  - Capture Cycle
    790
  - Capture Signal (SCS = 1)
    790
  - Output Modes
    791
  - Output Example - Timer in up Mode
    792
  - Output Example - Timer in Continuous Mode
    793
  - Output Example - Timer in Up/Down Mode
    794
  - Timer_A Registers
    796
  - Taxctl Register
    797
  - Taxctl Register Description
    797
  - Taxr Register
    798
  - Taxr Register Description
    798
  - Taxcctl0 to Taxcctl6 Register
    799
  - Taxcctl0 to Taxcctl6 Register Description
    799
  - Taxccr0 to Taxccr6 Register
    801
  - Taxccr0 to Taxccr6 Register Description
    801
  - Taxiv Register
    801
  - Taxiv Register Description
    801
  - Taxex0 Register
    802
  - Taxex0 Register Description
    802
  - RTC_C Block Diagram
    805
  - RTC_C Offset Error Calibration and Temperature Compensation
    811
  - RTC_C Registers
    814
  - RTCCTL0_L Register
    815
  - RTCCTL0_H Register
    816
  - RTCCTL1 Register
    817
  - RTCCTL1 Register Description
    817
  - RTCCTL3 Register
    818
  - RTCCTL3 Register Description
    818
  - RTCOCAL Register
    819
  - RTCOCAL Register Description
    819
  - RTCTCMP Register
    820
  - RTCTCMP Register Description
    820
  - RTCSEC Register
    821
  - RTCSEC Register Description
    821
  - RTCMIN Register
    822
  - RTCMIN Register Description
    822
  - RTCHOUR Register
    823
  - RTCHOUR Register Description
    823
  - RTCDAY Register
    824
  - RTCDAY Register Description
    824
  - RTCDOW Register
    824
  - RTCDOW Register Description
    824
  - RTCMON Register
    825
  - RTCMON Register Description
    825
  - RTCYEAR Register
    826
  - RTCYEAR Register Description
    826
  - RTCAMIN Register
    827
  - RTCAMIN Register Description
    827
  - RTCAHOUR Register
    828
  - RTCAHOUR Register Description
    828
  - RTCADAY Register
    829
  - RTCADAY Register Description
    829
  - RTCADOW Register
    829
  - RTCADOW Register Description
    829
  - RTCPS0CTL Register
    830
  - RTCPS0CTL Register Description
    830
  - RTCPS1CTL Register
    831
  - RTCPS0 Register
    832
  - RTCPS0 Register Description
    832
  - RTCPS1 Register
    832
  - RTCPS1 Register Description
    832
  - RTCIV Register
    833
  - RTCIV Register Description
    833
  - RTCBCD2BIN Register
    834
  - RTCBCD2BIN Register Description
    834
  - RTCBIN2BCD Register
    834
  - RTCBIN2BCD Register Description
    834
  - REF_A Block Diagram
    836
  - REFCTL0 Register
    840
  - REFCTL0 Register Description
    840
  - Precision ADC Block Diagram
    844
  - Analog Multiplexer
    846
  - Extended Sample Mode in 14-Bit Mode
    847
  - Pulse Sample Mode in 14-Bit Mode
    848
  - Sample & Conversion Time
    848
  - Analog Input Equivalent Circuit
    849
  - Precision ADC Differential Input Structure (Conceptual Diagram)
    849
  - Conversion Mode Summary
    850
  - Precision ADC Conversion Result Formats
    850
  - Single-Channel Single-Conversion Mode
    851
  - Sequence-Of-Channels Mode
    852
  - Repeat-Single-Channel Mode
    853
  - Repeat-Sequence-Of-Channels Mode
    854
  - Typical Temperature Sensor Transfer Function
    856
  - Precision ADC Grounding and Noise Considerations
    857
  - 22.3 ADC14 Registers
    859
  - ADC14CTL0 Register
    860
  - ADC14CTL0 Register Description
    861
  - ADC14CTL1 Register
    863
  - ADC14CTL1 Register Description
    864
  - ADC14LO0 Register
    865
  - ADC14LO0 Register Description
    865
  - ADC14HI0 Register
    866
  - ADC14HI0 Register Description
    866
  - ADC14LO1 Register
    867
  - ADC14LO1 Register Description
    867
  - ADC14HI1 Register
    868
  - ADC14HI1 Register Description
    868
  - ADC14MCTL0 to ADC14MCTL31 Register
    869
  - ADC14MCTL0 to ADC14MCTL31 Register Description
    869
  - ADC14MEM0 to ADC14MEM31 Register
    871
  - ADC14MEM0 to ADC14MEM31 Register Description
    871
  - ADC14IER0 Register
    872
  - ADC14IER0 Register Description
    872
  - ADC14IER1 Register
    875
  - ADC14IER1 Register Description
    875
  - ADC14IFGR0 Register
    876
  - ADC14IFGR0 Register Description
    877
  - ADC14IFGR1 Register
    880
  - ADC14IFGR1 Register Description
    880
  - ADC14CLRIFGR0 Register
    881
  - ADC14CLRIFGR0 Register Description
    882
  - ADC14CLRIFGR1 Register
    884
  - ADC14CLRIFGR1 Register Description
    884
  - ADC14IV Register
    885
  - ADC14IV Register Description
    886
  - COMP_E Block Diagram
    888
  - COMP_E Sample-And-Hold
    890
  - RC-Filter Response at the Output of the Comparator
    891
  - Reference Generator Block Diagram
    891
  - Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer
    892
  - Temperature Measurement System
    893
  - Timing for Temperature Measurement Systems
    893
  - Cexctl0 Register
    896
  - Cexctl0 Register Description
    896
  - Cexctl1 Register
    897
  - Cexctl1 Register Description
    897
  - Cexctl2 Register
    898
  - Cexctl2 Register Description
    898
  - Cexctl3 Register
    899
  - Cexctl3 Register Description
    899
  - Cexint Register
    901
  - Cexint Register Description
    901
  - Cexiv Register
    902
  - Cexiv Register Description
    902
  - Eusci_Ax Block Diagram - UART Mode (UCSYNC = 0)
    905
  - Character Format
    906
  - Idle-Line Format
    907
  - Address-Bit Multiprocessor Format
    908
  - Auto Baud-Rate Detection - Break/Synch Sequence
    909
  - Auto Baud-Rate Detection - Synch Field
    909
  - UART Vs Irda Data Format
    910
  - Receive Error Conditions
    911
  - Glitch Suppression, Eusci_A Receive Not Started
    912
  - BITCLK Baud-Rate Timing with UCOS16
    913
  - Modulation Pattern Examples
    913
  - BITCLK16 Modulation Pattern
    914
  - Receive Error
    917
  - BRCLK /Baud Rate
    918
  - Recommended Settings for Typical Crystals and Baud Rates
    918
  - UART State Change Interrupt Flags
    920
  - 24.4 Eusci_A UART Registers
    922
  - Ucaxctlw0 Register
    923
  - Ucaxctlw0 Register Description
    923
  - Ucaxctlw0 Register Description
    924
  - Ucaxctlw1 Register
    924
  - Ucaxctlw1 Register Description
    924
  - Ucaxbrw Register
    925
  - Ucaxbrw Register Description
    925
  - Ucaxmctlw Register
    925
  - Ucaxmctlw Register Description
    925
  - Ucaxstatw Register
    926
  - Ucaxstatw Register Description
    926
  - Ucaxrxbuf Register
    927
  - Ucaxrxbuf Register Description
    927
  - Ucaxtxbuf Register
    927
  - Ucaxtxbuf Register Description
    927
  - Ucaxabctl Register
    928
  - Ucaxabctl Register Description
    928
  - Ucaxirctl Register
    929
  - Ucaxirctl Register Description
    929
  - Ucaxie Register
    930
  - Ucaxie Register Description
    930
  - Ucaxifg Register
    931
  - Ucaxifg Register Description
    931
  - Ucaxiv Register
    932
  - Ucaxiv Register Description
    932
  - Eusci Block Diagram - SPI Mode
    935
  - Ucxste Operation
    936
  - Character Format
    937
  - Eusci Master and External Slave (UCSTEM = 0)
    937
  - Master Mode
    937
  - Eusci Slave and External Master
    938
  - Slave Mode
    938
  - Serial Clock Control
    939
  - SPI Enable
    939
  - Eusci SPI Timing with UCMSB
    940
  - SPI Interrupts
    940
  - Using the SPI Mode with Low-Power Modes
    940
  - Eusci_A SPI Registers
    942
  - Ucaxctlw0 Register
    943
  - Ucaxbrw Register
    944
  - Ucaxbrw Register Description
    944
  - Ucaxstatw Register
    945
  - Ucaxstatw Register Description
    945
  - Ucaxrxbuf Register
    946
  - Ucaxrxbuf Register Description
    946
  - Ucaxtxbuf Register
    947
  - Ucaxtxbuf Register Description
    947
  - Ucaxie Register
    948
  - Ucaxie Register Description
    948
  - Ucaxifg Register
    949
  - Ucaxifg Register Description
    949
  - Ucaxiv Register Description
    950
  - 25.5 Eusci_B SPI Registers
    951
  - Ucaxiv Register 25.5 Eusci_B SPI Registers
    951
  - Ucbxctlw0 Register
    952
  - Ucbxctlw0 Register Description
    952
  - Ucbxbrw Register
    953
  - Ucbxbrw Register Description
    953
  - Ucbxstatw Register
    953
  - Ucbxstatw Register Description
    953
  - Ucbxrxbuf Register
    954
  - Ucbxrxbuf Register Description
    954
  - Ucbxtxbuf Register
    954
  - Ucbxtxbuf Register Description
    954
  - Ucbxie Register
    955
  - Ucbxie Register Description
    955
  - Ucbxifg Register
    955
  - Ucbxifg Register Description
    955
  - Ucbxiv Register
    956
  - Ucbxiv Register Description
    956
  - Eusci_B Block Diagram - I
    959
  - Bus Connection Diagram
    960
  - Eusci_B Initialization and Reset
    960
  - I 2 C Serial Data
    960
  - Addressing Modes
    961
  - Bit Transfer on I
    961
  - I2C Master 10-Bit Addressing Mode
    961
  - Module 7-Bit Addressing Format
    961
  - Module Data Transfer
    961
  - C Module Addressing Format with Repeated START Condition
    962
  - Module 10-Bit Addressing Format
    962
  - Time-Line Legend
    962
  - Slave Transmitter Mode
    963
  - C Slave Receiver Mode
    964
  - C Slave 10-Bit Addressing Mode
    965
  - C Master Transmitter Mode
    967
  - I 2 C Master Receiver Mode
    969
  - Arbitration Procedure between Two Master Transmitters
    971
  - C Module Operating Modes 26.3.5 Glitch Filtering
    972
  - Clock Generators During Arbitration
    972
  - Glitch Filter Length Selection Bits
    972
  - Synchronization of Two I
    972
  - C Clock Generation and Synchronization 26.3.7 Byte Counter
    973
  - Multiple Slave Addresses
    974
  - Eusci_B Interrupts in I C Mode
    975
  - Mode with Low-Power Modes
    975
  - State Change Interrupt Flags
    975
  - 26.4 Eusci_B I2C Registers
    977
  - 26.4.1 Ucbxctlw0 Register
    978
  - Ucbxctlw0 Register Description
    978
  - 26.4.2 Ucbxctlw1 Register
    980
  - Ucbxctlw1 Register Description
    980
  - 26.4.3 Ucbxbrw Register
    982
  - 26.4.4 Ucbxstatw
    982
  - Ucbxbrw Register Description
    982
  - Ucbxstatw Register
    982
  - 26.4.5 Ucbxtbcnt Register
    983
  - Ucbxtbcnt Register Description
    983
  - 26.4.6 Ucbxrxbuf Register
    984
  - 26.4.7 Ucbxtxbuf
    984
  - Ucbxtxbuf Register
    984
  - 26.4.8 Ucbxi2Coa0 Register
    985
  - 26.4.10 Ucbxi2Coa2 Register
    986
  - 26.4.9 Ucbxi2Coa1 Register
    986
  - 26.4.11 Ucbxi2Coa3 Register
    987
  - 26.4.12 Ucbxaddrx Register
    987
  - 26.4.13 Ucbxaddmask Register
    988
  - 26.4.14 Ucbxi2Csa Register
    988
  - Ucbxi2Csa Register Description
    988
  - 26.4.15 Ucbxie Register
    989
  - Ucbxie Register Description
    989
  - 26.4.16 Ucbxifg Register
    991
  - Ucbxifg Register Description
    991
  - 26.4.17 Ucbxiv Register
    993
  - Ucbxiv Register Description
    993
- Reset Status and Override Control
  274
- Mode
  
  957
  - Enhanced Universal Serial Communication Interface B (Eusci_B) Overview
    958
  - Mode
    958
  - Mode
    959
- LCD_F Controller
  
  994
  - LCD_F Registers
    994
    
    27.1 LCD_F Controller Introduction
    995
    
    27.1.1 Introduction
    995
    
    27.1.2 Features
    995
  - Differences Among LCD_B, LCD_C, LCD_E and LCD_F
    995
    
    27.1.3 Functional Block Diagram
    996
  - LCD_F Controller Block Diagram
    996
    
    27.2 LCD_F Controller Architecture and Operation
    997
    
    27.2.1 Power Management
    997
    
    27.2.2 Clock System
    997
    
    27.2.3 Interrupts
    997
    
    27.2.4 Memory
    998
    
    27.2.5 LCD_F Functional Operation
    999
  - LCD Memory - Example for 96 Segments
    999
  - Lcdmx COM Assignment
    1000
  - Animation Memory
    1003
  - Bias Generation, Static, 1/2 and 1/3 Bias, for Static, 2-Mux to 4-Mux
    1004
  - Bias Generation for 5-Mux to 8-Mux Mode, 1/3-Bias and 1/4-Bias in LCD
    1005
  - Bias Voltages and External Pins
    1006
  - LCD Voltage and Biasing Characteristics
    1006
  - Example Static Waveforms
    1007
  - Example 2-Mux Waveforms
    1008
  - Example 3-Mux Waveforms
    1009
  - Example 4-Mux Waveforms
    1010
  - Example 6-Mux Waveforms
    1011
  - Example 8-Mux, 1/3 Bias Waveforms (LCDLP = 0)
    1012
  - Example 8-Mux, 1/3 Bias Low-Power Waveforms (LCDLP = 1)
    1013
  - Example 8-Mux, 1/4 Bias Waveforms (LCDLP = 0)
    1014
    
    27.3 LCD_F Registers
    1015
  - LCD_F Memory Registers
    1016
  - LCD_F Blinking Memory Registers
    1018
  - LCD_F Animation Memory Registers
    1020
    
    27.3.1 LCDCTL Register
    1021
  - LCDCTL Register Description
    1021
    
    27.3.2 LCDBMCTL Register
    1023
  - LCDBMCTL Register Description
    1023
    
    27.3.3 LCDVCTL Register
    1025
  - LCDVCPCTL Register
    1025
  - LCDVCTL Register Description
    1025
    
    27.3.4 LCDPCTL0 Register
    1026
  - LCDPCTL0 Register Description
    1026
    
    27.3.5 LCDPCTL1 Register
    1030
  - LCDPCTL1 Register Description
    1030
    
    27.3.6 LCDCSSEL0 Register
    1034
  - LCDCSSEL0 Register Description
    1034
    
    27.3.7 LCDCSSEL1 Register
    1037
  - LCDCSSEL1 Register Description
    1037
    
    27.3.8 LCDANMCTL Register
    1040
  - LCDANMCTL Register Description
    1040
    
    LCDIE Register
    1042
  - LCDIE Register Description
    1042
    
    LCDIFG Register
    1043
  - LCDIFG Register Description
    1043
    
    LCDSETIFG Register
    1044
  - LCDSETIFG Register Description
    1044
    
    LCDCLRIFG Register
    1045
  - LCDCLRIFG Register Description
    1045
    
    Lcdm[Index] Register
    1046
  - Lcdm[Index] Register Description
    1046
    
    Lcdbm[Index] Register
    1048
  - Lcdbm[Index] Register Description
    1048
    
    Lcdanm[Index] Register
    1050
  - Lcdanm[Index] Register Description
    1050
- Revision History
  
  1052

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