Samsung KS57C2308 Manual page 192

INTERRUPTS
+ +
PROGRAMMING TIP — Setting the INT Interrupt Priority
The following instruction sequence sets the INT1 interrupt to high priority:
BITS
SMB
DI
LD
LD
EI
EXTERNAL INTERRUPT 0 AND 1 MODE REGISTERS (IMOD0 and IMOD1)
The following components are used to process external interrupts at the INT0 and INT1 pins:
— Noise filtering circuit for INT0
— Edge detection circuit
— Two mode registers, IMOD0 and IMOD1
The mode registers are used to control the triggering edge of the input signal. IMOD0 and IMOD1 settings let you
choose either the rising or falling edge of the incoming signal as the interrupt request trigger. The INT4 interrupt
is an exception since its input signal generates an interrupt request on both rising and falling edges. Since INT2 is
a qusi-interrupt, the interrupt request flag (IRQ2) must be cleared by software.
FB4H IMOD0.3
FB5H "0"
FB6H "0"
IMOD0, IMOD1 and IMOD2 are addressable by 4-bit write instructions.
zero, selecting rising edges as the trigger for incoming interrupt requests.
IMOD0 IMOD0.3
0
1
IMOD1 0
7-8
EMB
15
A,#3H
IPR,A
"0" IMOD0.1
"0" "0"
IMOD2.2 IMOD2.1
Table 7-5. IMOD0 and IMOD1 Register Organization
0 IMOD0.1
0
0
1
1
0 0
; IPR.3 (IME) 0
; IPR.3 (IME) 1
IMOD0.0
IMOD1.0
IMOD2.0
RESET
IMOD0.0
Select CPU clock for sampling
Select fxx/64 sampling clock
0 Rising edge detection
1 Falling edge detection
0 Both rising and falling edge detection
1 IRQ0 flag cannot be set to "1"
IMOD1.0 Effect of IMOD1 and IMOD2 Settings
0 Rising edge detection
1 Falling edge detection
KS57C2308/P2308/C2316/P2316
clears all IMOD values to logic
Effect of IMOD0 Settings