Table of Contents
Advertisement
Unbuffered SODIMM
[ Table 17 ] Timing Parameters by Speed Bin (Cont.)
Speed
Parameter
Power Down Timing
Exit Power Down with DLL on to any valid com-
mand;Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to com-
mands requiring a locked DLL
CKE minimum pulse width
Command pass disable delay
Power Down Entry to Exit Timing
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Timing of WR command to Power Down entry
(BC4MRS)
Timing of WRA command to Power Down entry
(BC4MRS)
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT Timing
ODT high time without write command or with write
command and BC4
ODT high time with Write command and BL8
Asynchronous RTT turn-on delay (Power-Down with
DLL frozen)
Asynchronous RTT turn-off delay (Power-Down with
DLL frozen)
RTT turn-on
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference
RTT dynamic change skew
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining
mode is programmed
DQS/DQS delay after tDQS margining mode is pro-
grammed
Write leveling setup time from rising CK, CK crossing to
rising DQS, DQS crossing
Write leveling hold time from rising DQS, DQS crossing
to rising CK, CK crossing
Write leveling output delay
Write leveling output error
datasheet
DDR3-800
Symbol
MIN
MAX
max
tXP
(3nCK,
-
7.5ns)
max
tXPDLL
(10nCK,
-
24ns)
max
tCKE
(3nCK,
-
7.5ns)
tCPDED
1
-
tPD
tCKE(min)
9*tREFI
tACTPDEN
1
-
tPRPDEN
1
-
tRDPDEN
RL + 4 +1
-
WL + 4
tWRPDEN
+(tWR/
-
tCK(avg))
WL + 4
tWRAPDEN
-
+WR +1
WL + 2
tWRPDEN
+(tWR/
-
tCK(avg))
WL +2 +WR
WL +2 +WR
tWRAPDEN
-
+1
tREFPDEN
1
-
tMRSPDEN
tMOD(min)
-
ODTH4
4
-
ODTH8
6
-
tAONPD
2
8.5
tAOFPD
2
8.5
tAON
-400
400
tAOF
0.3
0.7
tADC
0.3
0.7
tWLMRD
40
-
tWLDQSEN
25
-
tWLS
325
-
tWLH
325
-
tWLO
0
9
tWLOE
0
2
DDR3-1066
DDR3-1333
MIN
MAX
MIN
max
max
(3nCK,
-
(3nCK,6ns)
7.5ns)
max
max
(10nCK,
-
(10nCK,
24ns)
24ns)
max
max
(3nCK,
-
(3nCK,
5.625ns)
5.625ns)
1
-
1
tCKE(min)
9*tREFI
tCKE(min)
1
-
1
1
-
1
RL + 4 +1
-
RL + 4 +1
WL + 4
WL + 4
+(tWR/
-
+(tWR/
tCK(avg))
tCK(avg))
WL + 4
WL + 4 +WR
-
+WR +1
+1
WL + 2
WL + 2
+(tWR/
-
+(tWR/
tCK(avg))
tCK(avg))
WL +2 +WR
-
+1
+1
1
-
1
tMOD(min)
-
tMOD(min)
4
-
4
6
-
6
2
8.5
2
2
8.5
2
-300
300
-250
0.3
0.7
0.3
0.3
0.7
0.3
40
-
40
25
-
25
245
-
195
245
-
195
0
9
0
0
2
0
- 28 -
DDR3 SDRAM
DDR3-1600
Units
MAX
MIN
MAX
max
-
-
(3nCK,6ns)
max
-
(10nCK,
-
24ns)
max
-
-
(3nCK,5ns)
-
1
-
nCK
9*tREFI
tCKE(min)
9*tREFI
tCK
-
1
-
nCK
-
1
-
nCK
-
RL + 4 +1
-
WL + 4
-
+(tWR/
-
nCK
tCK(avg))
WL + 4 +WR
-
-
nCK
+1
WL + 2
-
+(tWR/
-
nCK
tCK(avg))
WL +2 +WR
-
-
nCK
+1
-
1
-
-
tMOD(min)
-
-
4
-
nCK
-
6
-
nCK
8.5
2
8.5
ns
8.5
2
8.5
ns
250
-225
225
ps
tCK(avg
0.7
0.3
0.7
)
tCK(avg
0.7
0.3
0.7
)
-
40
-
tCK
-
25
-
tCK
-
165
-
ps
-
165
-
ps
9
0
7.5
ns
2
0
2
ns
Rev. 1.0
NOTE
2
15
20
20
9
10
9
10
20,21
7,f
8,f
f
3
3
Advertisement
Table of Contents
