Line Load Process; Instruction Presence Check And I-Cache Response - Texas Instruments TMS320VC5501 Instruction Cache

Introduction
Table 2.

Instruction Presence Check and I-Cache Response

Case 2-Way Cache
1 Miss
2 Hit
1.2.3

Line Load Process

14 Instruction Cache
Presence I-Cache Response
False 2-way cache line loaded from external memory,
requested 32-bit word delivered to CPU
True Requested 32-bit word taken directly from 2-way cache
When an instruction presence check results in a fetch from the external
memory, the 4-word external memory block that contains the requested word
is fetched and loaded into a line in the I-Cache. This line load process is
illustrated in Figure 4. The I-Cache uses the external memory interface (EMIF)
to fetch the 4-word block that contains the requested word. These four 32-bit
words are written to the line in the I-Cache one word at a time. The I-Cache
delivers the requested word to the CPU as soon as the word arrives in the data
array, even if the rest of the line is still being loaded. When the entire line is
loaded in the data array, the corresponding tag is written to the tag array and
the line valid bit is set to validate the line.
SPRU630C