Samsung S3C6400X User Manual page 128

SROM CONTROLLER
DataWidth2 [8]
ByteEnable1 [7]
WaitEnable1 [6]
Reserved [5]
DataWidth1 [4]
ByteEnable0 [3]
[2]
WaitEnable0
Reserved [1]
[0]
DataWidth0
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
6-6
Specifications and information herein are subject to change without notice.
Data bus width control for Memory Bank2
0 = 8-bit
nWBE / nBE(for UB/LB) control for Memory Bank1
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
Wait enable control for Memory Bank1
0 = WAIT disable
Reserved
Data bus width control for Memory Bank1
0 = 8-bit
nWBE / nBE(for UB/LB) control for Memory Bank0
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
Wait enable control for Memory Bank0
0 = WAIT disable
Reserved
Data bus width control for Memory Bank0.
Reset value is configured by OM setting.
0 = 8-bit
S3C6400X RISC MICROPROCESSOR
1 = 16-bit
1 = WAIT enable
1 = 16-bit
1 = WAIT enable
1 = 16-bit
0
0
0
0
0
0
0
0
H/W Set