Samsung S3C6400X User Manual page 57

SYSTEM CONTROLLER
Power domain in S3C6400X
S3C6400X consists of several power domains as shown in Figure 3-1. Sub-power domains, DOMAIN-V,
DOMAIN-I, DOMAIN-P, DOMAIN-F, and DOMAIN-S, are controlled by NORMAL_CFG and STOP_CFG. When
S3C6400X runs at NORMAL or IDLE mode, NORMAL_CFG controls them. If the controlled bit is clear,
corresponding block goes power-gating mode and lost previous state. Thus, user software must store internal
state before clearing the corresponding bit. When S3C6400x changes to STOP or DEEP-STOP mode, sub-power
domains automatically changes to power-gating mode.
STOP_CFG only controls ARM1176 and top module. If user software requires fast response time, the memory
and logic of ARM1176 must be set and retained during STOP mode. In this case, the logic power of top block
should be set and the memory power of top block can be configured. Otherwise, S3C6400X may not return to the
previous state. ARM1176 leakage current can be minimized when ARM1176 power is OFF (bit 29 and 17 of
STOP_CFG are '0'.) This configuration is called as DEEP-STOP mode. User software must store program status
information including internal registers, CPSR, SPSR and etc, before going to DEEP-STOP mode.
NORMAL/IDLE mode
In NORMAL mode, ARM1176 core, media co-processors, and all peripherals can operate fully. Typical system-
bus operating frequency is up to 133MHz. The clock to each media co-processors and peripherals can be
stopped selectively by software to reduce power consumption. The ON/OFF clock gating of the individual clock
source of each IP block is performed by controlling of each corresponding clock enable bit, which is specified by
HCLK_GATE, PCLK_GATE, and SCLK_GATE configuration registers.
In IDLE mode, ARM1176 is stopped without any change of other IP's. Typically, ARM1176 waits a wake-up event
to return to NORMAL mode.
All IP's can run at maximum operating frequency at NORMAL/IDLE mode. When some IP's are unnecessary to
run, S3C6400X can cut supply power using internal power-gating circuitry. As shown in Figure 3-14, five power
domains can be independently controlled with NORMAL_CFG configuration register. When all functional IP's are
unnecessary to run, user software can cut supply power of the corresponding power domain, whose color is grey
in Figure 3-14. All internal status of the corresponding domain will be lost after the corresponding power domain is
OFF. Thus, user software must store all information, which is required to restore internal state.
Figure 3-14. Power domains at NORMAL/IDLE mode (grey colored domain can be ON/OFF by
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
3-12
Specifications and information herein are subject to change without notice.
DOMAIN DOMAIN DOMAIN
V I P
AXI (64b)
DOMAIN
DOMAIN
X
ARM11
T
AXI (32b)
APB (32b)
PERIPHERAL
NORMAL_CFG configuration register)
S3C6400X RISC MICROPROCESSOR
DOMAIN
MEMSYS
F
DOMAIN DOMAIN
M S