Mc68030 Versus Mc68020 Dynamic Bus Sizing; Cache Filling - Motorola MC68030 User Manual

7.2.5 MC68030 versus MC68020 Dynamic Bus Sizing
The MC68030 supports the dynamic bus sizing mechanism of the MC68020
for asynchronous bus cycles (terminated with DSACKx) with two restrictions.
First, for a cachable access within the boundaries of an aligned long word,
the port size must be consistent throughout the transfer of each long word.
For example, when a byte port resides at address $00, addresses $01, $02,
and $03 must also correspond to byte ports. Second, the port must supply
as much data as it signals as port size, regardless of the transfer size indicated
with the size signals and the address offset indicated by AO and A 1 for
cachable accesses. Otherwise, dynamic bus sizing is identical in the two
processors.
7.2.6 Cache Filling
7-24
The on-chip data and instruction caches, described in SECTION 6 ON-CHIP
CACHE MEMORIES, are each organized as 16 lines of four long-word entries
each. For each line, a tag contains the most significant bits of the logical
address, FC2 (instruction cache) or FCO-FC2 (data cache), and a valid bit for
each entry in the line. An entry fill operation loads an entire long word
accessed from memory into a cache entry. This type of fill operation is per-
formed when one entry of a line is not valid and an access is cachable. A
burst fill operation is requested when a tag miss occurs for the current cycle
or when all four entires in the cache line are invalid (provided the cache is
enabled and burst filling for the cache is enabled). The burst fill operation
attempts to fill all four entries in the line. To support burst filling, the slave
device must have a 32-bit port and must have a burst mode capability; that
is, it must acknowledge a burst request with the cache burst acknowledge
(CBACK) signal. It must also terminate the burst accesses with STERM and
place a long word on the data bus for each transfer. The device may continue
to supply successive long words, asserting STERM with each one, until the
cache line is full. For further information about filling the cache, both entry
fills and burst mode fills, refer to 6.1.3 Cache Filling, 7.3.4 Synchronous Read
Cycle, 7.3.5 Synchronous Write Cycle, and 7.3.7 Burst Operation Cycles, which
discuss in detail the required bus cycles.
MC68030 USER'S MANUAL MOTOROLA