Pin Description - Denon S-301 Service Manual

PIN DESCRIPTION

No. Name I/O
−
1 VDDL
2 SEL1FS I
3 SEL4FS I
4 SELEXT I
5 DSGAIN I
6 XMTPCM I
−
7 VDDH
8 TEST1 I
9 TEST2 I
10 TEST3 I
11 TOUT1 O
−
12 VSS
−
13 VDDL
14 DIRPCK I
15 FMTPCM I
−
16 VSS
17 MCKOUT O
−
18 VDDH
19 PBCK I/O
20 PLRCK I/O
21 POSLR O
22 POCSW O
23 POFLR O
−
24 VSS
−
25 VDDL
26 TOUT2 O
27 MCK I
−
28 VSS
29 EXIMCK I
−
30 VDDH
31 EXIBCK I
32 EXILRCK I
33 EXISLR I
34 EXICSW I
35 EXIFLR I
−
36 VSS
−
37 VDDL
38 DSBCK I/O
Input
1
Property
voltage
−
2.5V Core power supply
PCM output rate select 1
PD 3.3V
L: 2fs/4fs, H: fs
PCM output rate select 2
PD 3.3V
L: 2fs, H: 4fs
fs/2fs/4fs output and external data output select
PD 3.3V
L: fs/2fs/4fs data, H: external data (EXI**)
DSD signal gain setting
PD 3.3V
L: 100% modulation = 0dB, H: 50% modulation = 0dB
PCM output mute control input
PD 3.3V
L: Mute ON, H: Mute OFF
−
3.3V I/O power supply
PD 3.3V Test input 1 (must be open or tie LOW for normal operation)
PD 3.3V Test input 2 (must be open or tie LOW for normal operation)
PD 3.3V Test input 3 (must be open or tie LOW for normal operation)
− −
Test output 1
− −
Ground
−
2.5V Core power supply
PCM output PBCK/PLRCK I/O select
PD 3.3V
L: Output (master mode), H: Input (slave mode)
PCM output format select
PD 3.3V
L: MSB-first left-justified 32-bit, H: IIS 32-bit
− −
Ground
−
12mA System clock output (selected by SELEXT)
−
3.3V I/O power supply
S, 6mA 3.3V PCM output BCK bit clock
S, 6mA 3.3V PCM output LRCK word clock
−
2mA PCM data output: surround left/right-channel
−
2mA PCM data output: center/subwoofer channel
−
2mA PCM data output: front left/right-channel
− −
Ground
−
2.5V Core power supply
− −
Test output 2
−
3.3V Master clock input: 512fs (22.5792MHz, fs = 44.1kHz)
− −
Ground
−
3.3V External system clock input
−
3.3V I/O power supply
S 3.3V External PCM data BCK bit clock input
S 3.3V External PCM data LRCK word clock input
−
3.3V External PCM data input: surround left/right-channel
−
3.3V External PCM data input: center/subwoofer channel
−
3.3V External PCM data input: front left/right-channel
− −
Ground
−
2.5V Core power supply
S, 6mA 3.3V DSD data input bit clock. Controlled by DIRDSCK
59
Description
S-301