Denon S-301 Service Manual page 19

Name Pin Numbers
DSCK 102
DCLK 105
YUV0
CAMIN2
UDAC
106
YUV1
107
VREF
YUV2
108
CDAC
YUV3
109
COMP
YUV4
110
RSET
ADVEE 111
( )
I/O Definition
O Output clock to DRAM.
I Clock input to PLL.
O YUV pixel 2 output data.
I Camera YUV 2.
O Video DAC output.
Pin
Value
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
F: CVBS/chroma signal for simultaneous mode.
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
O YUV pixel 1 output data.
I Internal voltage reference to video DAC. Bypass to ground with 0.1-µF capacitor.
O YUV pixel 2 output data.
O Video DAC output. Refer to description and matrix for UDAC pin 106.
O YUV pixel 3 output data.
I Compensation input. Bypass to ADVEE with 0.1-µF capacitor.
O YUV pixel 4 output data.
I DAC current adjustment resistor input.
P Analog power for video DAC.
115 114
F DAC V DAC
CVBS/Chroma CVBS1
CVBS/Chroma CVBS1
CVBS/Chroma N/A
CVBS/Chroma CVBS1
CVBS/Chroma CVBS1
CVBS/Chroma CVBS1
CVBS/Chroma N/A
N/A SYNC
CVBS/Chroma Chroma
CVBS CVBS1
CVBS CVBS1
N/A SYNC
CVBS/Chroma N/A
CVBS/Chroma CVBS1
Chroma Y
19
113 108 106
Y DAC C DAC U DAC
Y C N/A
Y C CVBS2
Y C N/A
N/A N/A CVBS2
N/A N/A N/A
Y Pb Pr
Y Pb Pr
G B R
Y Pb Pr
G B R
G R B
G R B
Y Pr Pb
Y Pr Pb
G R B
S-301