Denon S-301 Service Manual page 18

Name Pin Numbers
TSD0
33
SEL_PLL0
TSD1
36
SEL_PLL1
TSD2 37
TSD3 38
NC 48
MCLK 39
TBCK 40
SEL_PLL3
41
SPDIF_OUT
SPDIF_IN 42
RSD 45
RWS 46
RBCK 47
XIN 49
XOUT 50
AVEE 51
AVSS 52
DMA[11:0] 53:58, 61:66
DCAS# 69
DOE#
70
DSCK_EN
DWE# 71
DRAS# 72
DMBS0 73
DMBS1 74
DB[15:0] 77:82, 85:90, 93:96
DCS[1:0]# 97,100
DQM 101
( )
I/O Definition
O Audio transmit serial data port 0.
I Refer to the description and matrix for SEL_PLL2 pin 32.
O Audio transmit serial data port 1.
I Refer to the description and matrix for SEL_PLL2 pin 32.
O Audio transmit serial data output 2.
O Audio transmit serial data output 3.
— No connect pins. Leave open.
I/O Audio master clock for audio DAC.
O Audio transmit bit clock.
I Clock source select. Strapped to VCC or ground via 4.7-kΩ resistor; read only
during reset.
SEL_PLL3
O S/PDIF output.
I S/PDIF input.
I Audio receive serial data.
I Audio receive frame sync.
I Audio receive bit clock.
I 27-MHz crystal input.
O 27-MHz crystal output.
P Analog power for PLL.
G Analog ground for PLL.
O DRAM address bus.
O DRAM column address strobe.
O DRAM output enable (active-low).
O DRAM clock enable.
O DRAM write enable (active-low).
O DRAM row address strobe (active-low).
O DRAM bank select 0.
O DRAM bank select 1.
I/O DRAM data bus.
O DRAM chip select (active-low).
O Data input/output mask.
Clock Source
0 Crystal oscillator
1 DCLK input
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S-301