Pin Description - Denon S-301 Service Manual
Dvd home theater system
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Also See for S-301:
- Service manual (213 pages) ,
- Operating instructions manual (148 pages) ,
- Control protocol (32 pages)
Table of Contents
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PIN DESCRIPTION
No.
Name
1
VDDL
2
SEL1FS
3
SEL4FS
4
SELEXT
5
DSGAIN
6
XMTPCM
7
VDDH
8
TEST1
9
TEST2
10
TEST3
11
TOUT1
12
VSS
13
VDDL
14
DIRPCK
15
FMTPCM
TE
L 13942296513
16
VSS
17
MCKOUT
18
VDDH
19
PBCK
20
PLRCK
21
POSLR
22
POCSW
23
POFLR
24
VSS
25
VDDL
26
TOUT2
27
MCK
28
VSS
29
EXIMCK
30
VDDH
31
EXIBCK
32
EXILRCK
33
EXISLR
34
EXICSW
35
EXIFLR
36
VSS
www
37
VDDL
38
DSBCK
.
http://www.xiaoyu163.com
Input
1
I/O
Property
voltage
−
−
2.5V
I
PD
3.3V
I
PD
3.3V
I
PD
3.3V
I
PD
3.3V
I
PD
3.3V
−
−
3.3V
I
PD
3.3V
I
PD
3.3V
I
PD
3.3V
−
−
O
−
−
−
−
−
2.5V
I
PD
3.3V
I
PD
3.3V
−
−
−
−
O
12mA
−
−
3.3V
I/O
S, 6mA
3.3V
I/O
S, 6mA
3.3V
−
O
2mA
−
O
2mA
−
O
2mA
−
−
−
−
−
2.5V
−
−
O
−
I
3.3V
−
−
−
−
I
3.3V
−
−
3.3V
I
S
3.3V
I
S
3.3V
−
I
3.3V
−
I
3.3V
−
I
3.3V
−
−
−
−
−
2.5V
x
ao
u163
y
I/O
S, 6mA
3.3V
i
http://www.xiaoyu163.com
2 9
8
Description
Core power supply
PCM output rate select 1
L: 2fs/4fs, H: fs
PCM output rate select 2
L: 2fs, H: 4fs
fs/2fs/4fs output and external data output select
L: fs/2fs/4fs data, H: external data (EXI**)
DSD signal gain setting
L: 100% modulation = 0dB, H: 50% modulation = 0dB
PCM output mute control input
L: Mute ON, H: Mute OFF
I/O power supply
Test input 1 (must be open or tie LOW for normal operation)
Test input 2 (must be open or tie LOW for normal operation)
Test input 3 (must be open or tie LOW for normal operation)
Test output 1
Ground
Core power supply
PCM output PBCK/PLRCK I/O select
L: Output (master mode), H: Input (slave mode)
PCM output format select
L: MSB-first left-justified 32-bit, H: IIS 32-bit
Q Q
3
6 7
1 3
1 5
Ground
System clock output (selected by SELEXT)
I/O power supply
PCM output BCK bit clock
PCM output LRCK word clock
PCM data output: surround left/right-channel
PCM data output: center/subwoofer channel
PCM data output: front left/right-channel
Ground
Core power supply
Test output 2
Master clock input: 512fs (22.5792MHz, fs = 44.1kHz)
Ground
External system clock input
I/O power supply
External PCM data BCK bit clock input
External PCM data LRCK word clock input
External PCM data input: surround left/right-channel
External PCM data input: center/subwoofer channel
External PCM data input: front left/right-channel
Ground
Core power supply
co
DSD data input bit clock. Controlled by DIRDSCK
.
59
9 4
2 8
0 5
8
2 9
9 4
2 8
m
S-301
9 9
9 9
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