Pin Description - Denon S-102 Service Manual

W9864G2GH-7 (IC402: 1U-3836)

PIN DESCRIPTION

PIN NAME FUNCTION
Address
A0−A10
BS0, BS1 Bank Select
Data Input/
DQ0−DQ31
Output
Chip Select
CS
Row Address
RAS
Strobe
Column Address
CAS
Strobe
Write Enable
WE
Input/output mask The output buffer is placed at Hi-Z (with latency of 2) when
DQM0−
DQM3
CLK Clock Inputs
CKE Clock Enable
V Power (+3.3V)
CC
V Ground
SS
V Power (+3.3V) for
CCQ
I/O buffer
V Ground for I/O
SSQ
buffer
NC No Connection
56
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0−A10. Column address: A0−A7.
A10 is sampled during a precharge command to determine if
all banks are to be precharged or bank selected by BS0, BS1.
Select bank to activate during row address latch time, or bank
to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
Command input. When sampled at the rising edge of the
clock RAS , CAS and WE define the operation to be
executed.
Referred to RAS
Referred to RAS
DQM is sampled high in read cycle. In write cycle, sampling
DQM high will block the write operation with zero latency.
System clock used to sample inputs on the rising edge of
clock.
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Separated power from V , to improve DQ noise immunity.
CC
Separated ground from V , to improve DQ noise immunity.
SS
No connection
S-102