Pin Configuration; Pin Function Description - Denon S-301 Service Manual

HY57V6432320DTP (IC404: 1U-3692)

PIN CONFIGURATION

V 1
DD
DQ0 2
V 3
DDQ
DQ1 4
DQ2 5
V 6
SSQ
DQ3 7
DQ4 8
V 9
DDQ
DQ5 10
DQ6 11
V 12
SSQ
DQ7 13
N.C 14
V 15
DD
16
DQM0
WE 17
CAS 18
RAS 19
CS 20
N.C 21
BA0 22
BA1 23
A10/AP 24
A0 25
A1 26
A2 27
DQM2 28
V 29
DD
30
N.C
DQ16 31
V 32
SSQ
DQ17 33
DQ18 34
V 35
DDQ
36
DQ19
DQ20 37
V 38
SSQ
DQ21 39
DQ22 40
V 41
DDQ
DQ23 42
V 43
DD

PIN FUNCTION DESCRIPTION

Pin
CLK System clock
CS Chip select
CKE Clock enable
A ~ A Address
0 10
BA0,1 Bank select address
RAS Row address strobe
CAS Column address strobe
WE Write enable
DQM0 ~ 3 Data input/output mask
DQ ~ Data input/output
0 31
V /V Power supply/ground
DD SS
V /V Data output power/ground
DDQ SSQ
NC No Connection
V
86
SS
DQ15
85
V BLOCK DIAGRAM
84
SSQ
DQ14
83
82 DQ13
V
81 DDQ
DQ12
80
DQ11
79
V
78 SSQ
77 DQ10
76 DQ9
V
75
DDQ
DQ8
74
73 N.C
V
72
SS
71 DQM1
CLK
N.C
70
N.C
69
68 CLK ADD
CKE
67
A9
66
65 A8
64 A7
A6
63
62 A5
LCKE
A4
61
A3
60
LRAS
59 DQM3
V
58 SS
57 N.C
56 DQ31
V
55
DDQ
DQ30
54
CLK
53 DQ29
V
52
SSQ
51 DQ28
DQ27
50
V
49
DDQ
48 DQ26
DQ25
47
V
46
SSQ
45 DQ24
44 V
SS
Name
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
Row/column addresses are multiplexed on the same pins.
Row address : RA
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No connection on the device.
Bank Select
LCBR LWE LCAS
Timing Register
CKE CS RAS CAS
Input Function
~ RA , Column address : CA
0 10
after the clock and masks the output.
SHZ
45
Data Input Register
512K x 32
512K x 32
512K x 32
512K x 32
Column Decoder
Latency & Burst Length
Programming Register
LWCBR LDQM
WE DQM
~ CA
0 7
S-301
LWE
LDQM
DQi