Pin Diagram; Block Diagrams - Denon S-301 Service Manual

FLI2310 (IC403: 1U-3692)

Pin Diagram

1
HSYNC1 PORT1
VSYNC1 PORT1
FIELD ID1 PORT1
IN CLK1 PORT1
5
HSYNC2 PORT1
VSYNC2 PORT1
FIELD ID2 PORT1
VDD1
VSS
1 0
IN CLK2 PORT1
B/Cb/D1 0
B/Cb/D1 1
B/Cb/D1 2
B/Cb/D1 3
1 5
B/Cb/D1 4
VDDcore1
VSScore
B/Cb/D1 5
B/Cb/D1 6
2 0
B/Cb/D1 7
R/Cr/Cb Cr 0
R/Cr/Cb Cr 1
R/Cr/Cb Cr 2
R/Cr/Cb Cr 3
2 5
R/Cr/Cb Cr 4
R/Cr/Cb Cr 5
R/Cr/Cb Cr 6
R/Cr/Cb Cr 7
G/Y/Y 0
3 0
VDD2
VSS
G/Y/Y 1
G/Y/Y 2
G/Y/Y 3
G/Y/Y 4 3 5
VDDcore2
VSScore
G/Y/Y 5
G/Y/Y 6
4 0
G/Y/Y 7
IN SEL
TEST
DEV ADDR1
DEV ADDR0
4 5
SCLK
SDATA
RESET N
VDD3
VSS
5 0
SDRAM DATA(0)
SDRAM DATA(1)
SDRAM DATA(2)

Block Diagrams

Port 2
8 bit
Input Processor
656 Input
with Auto Sync
and auto Adjust
Port 1
8/16/24 bit
RGB/YCrCb
Input
Clock
Generation
PLLs
Noise Reducer,
Vertical and
Deinterlacer, Frame
Rate Converter and
SDRAM interface
2Mx32
SDRAM
(external)
23
Output
Horizontal
Processor
Scalers
Vertical and
Horizontal
Enhancers
S-301
OE
1 5 5 G/Y/Y OUT 7
G/Y/Y OUT 6
G/Y/Y OUT 5
G/Y/Y OUT 4
G/Y/Y OUT 3
1 5 0 G/Y/Y OUT 2
G/Y/Y OUT 1
G/Y/Y OUT 0
VSS
VDD8
1 4 5
R/V/Pr OUT 7
R/V/Pr OUT 6
R/V/Pr OUT 5
R/V/Pr OUT 4
R/V/Pr OUT 3
1 4 0 R/V/Pr OUT 2
VSScore
VDDcore7
R/V/Pr OUT 1
R/V/Pr OUT 0
1 3 5 B/U/Pb OUT 7
B/U/Pb OUT 6
B/U/Pb OUT 5
B/U/Pb OUT 4
B/U/Pb OUT 3
1 3 0
B/U/Pb OUT 2
VSS
VDD7
B/U/Pb OUT 1
B/U/Pb OUT 0
1 2 5 CLKOUT
VSScore
VDDcore6
CTLOUT4
CTLOUT3
1 2 0 CTLOUT2
CTLOUT1
CTLOUT0
TEST OUT1
TEST OUT0
1 1 5
TEST3
SDRAM CLKIN
VSS
VDD6
SDRAM CLKOUT
1 1 0
SDRAM DQM
SDRAM CSN
SDRAM BA0
SDRAM BA1
SDRAM CASN
1 0 5 SDRAM RASN
16/20/24 bit
RBG/YCrCb
Digital Outputs