Hdmi-Board (2 Of 2) Block Diagram - Panasonic TH-103PF10UK Service Manual

TH-103PF10UK/EK

9.8. HDMI-Board (2 of 2) Block Diagram

! HDMI DIGITAL SIGNAL PROCESSOR
MICOM
HDMI INTERFACE
<TXNHHH10XXT>
(Exchange board only)
+9V
IC3322
AUDIO AMP_R
+9V
8
2
1
3
6
7
1
5
2
3
4
5
6
7
+5V_B +5V_A +5V
D3332 D3333 D3334
8
9
10
IC3329
+3.3VREG
BUFFER
5 VCC
IN_A
2
TH-103PF10UK
HDMI-Board (2 of 2) Block Diagram
IC3339
DC-DC CONVERTER
+15V
15V->3.3V
21 VIN OUT -1
IC3338
AVR+5V OUT -2
5 +5V 1 5 VCC LX
17 VDD -INC
VO
Q3329
FB
AMP
IC3323
AUDIO AMP_L
+9V
8
2
1
3
Q3328
6
AMP
7
5
IC3310
MAIN MICOM
127 HDMI_DAC_PDWN
+3.3VREG
ADIN1 112
IVDO
EX_RESERVE1
ADIN2 113
EX_RESERVE2
83 OSCXO ADIN3 114
X3302
EX_RESERVE3
ADIN4
10MHz 115
84 OSCXI
TV/LOAD_CMD_SCL
64
SCL1
TV/LOAD_CMD_SDA
63
SDA1
HDMI_A_MUTE 126
GENX_HR_EEP_SDA
39 SDA0
SIGTYPE0 5
GENX_HR_EEP_SCL
40 SCL0
45 HDMI_INT SIGTYPE3 8
68 HDMI_RST
RESERVE1 124
125
12
RESERVE6 15
GNX_LVDS_PWD 33
FPGA_RST 111
N_FHD 46
FHD
HPD1
56 HPD1 HDMI_5V_DET1 52
HPD2
57 HPD2 HDMI_5V_DET2 53
NBOOT 92
NRST 93
HD/FHD_DET
IC3330
+3.3VREG
BUFFER
5 VCC
OUT_Y OUT_Y
IN_A
4 2 4
15V
IC3321
EXPAND I/O
19
CH_SEL
4 P0 VCC 16
16 EX_RESERVE1
5 P1
SDA 15
EX_RESERVE2
G2 S2 G1 S1
6 P2
18
EX_RESERVE3
D2 D2 D1 D1
7 P3 SCL 16
13
Q3237
3.3V
23 +3.3VREG TP3334
24
Q3315
AUDIO
MUTE
Q3313
Q3314
INV.
AUDIO
MUTE
IC3344
CH_SEL
VDD VOUT
6 +2.5V 1
IC3342
VCC OUT
Q3312 2 +1.2V 4
A-MUTE
(CONTROL BUS)
HD
Y0,Y1,UV0,UV1
HDMI_5V_DET1
Y2-Y9
HDMI_5V_DET2
UV2-UV9
CLK TP3346
GENX_NBOOT
DCK
VS TP3343
VSYNC
HS TP3345
HSYNC
DE TP3344
DE
EDID_WP
IC3343 FIN 1
CPG S2 2
S1 3
S0 4
FOUT 6
S3 7
VDD 8
IC3312
RESET
+3.3VREG
1 8
VOUT VDD
74
+5VSTB
IC3319
SLOT_SRQ
VCC 8
CONFIG SLOT_SDA
SDA 5
ROM
SLOT_SCL CMD_SCL
SCL 6
CMD_SDA
WP
7
SLOT_SCL
+5VSTB
SLOT_SDA
GENX_NBOOT
SLOT_SDA
SLOT_SCL
PLUG_DET
HDMI_R
HDMI_L
SLOT_SCL
SLOT_SDA
HD/FHD_DET
SLOT_SRQ
+5VSTB
5VSTB
+9V
9V
+3.3VREG
VCCI01,03,04
+2.5V
VCC02
+5V
5V
IC3341
FPGA
+1.2V
VCCA_PLL1,2
LVDS18p
LVDS18n
LVDS23p
LVDS23n
SYG_TYPE0
LVDS27p
LVDS27n
SYG_TYPE3
LVDS31p
LVDS31n
RESERVE1
LVDS34p
RESERVE6 LVDS34n
GENX_L YDS_PWD
LVDS26p
FPGA_RST LVDS26n
N_FHD
LVDS37p
Y0,Y1
UV0,UV1 LVDS37n
LVDS19p
Y2-Y9
LVDS19n
LVDS28p
UV2-UV9
LVDS28n
DP_CLK
LVDS33p
LVDS33n
VS
LVDS35p
HS LVDS35n
DE
IC3314
HDMI_5V_DET1
+3.3VREG
CONFIG ROM(FPGA)
HDMI_5V_DET2
EDID_WP
3 VCC
DCLK 6 DCLK
O_CLK
+3.3VREG
S2 ASDO 5 ASDI
S1
DATAO 2 DATA
S0
nCSO 1 NCS
CLK1
S3
CLK4
CONFIG_DONE
nCE
nCONFIG
TH-103PF10UK
HDMI-Board (2 of 2) Block Diagram
FOR
FACTORY
H3
USE
1 +5V
2 SRQ
3 GND
4 TVLOAD_CMD_SCL
5 TVLOAD_CMD_SDA
6 SLOT_SCL
7 SLOT_SDA
8 H_WP
9 GENX_BOOT
TO
H1
DS12
PLUG DET
B39
+15V
B38
B37 +15V
B28 PLUG DET
A28 HDMI_R
A26 HDMI_L
B25 SLOT_SCL
B24 SLOT_SDA
A23 HD/FHD DET
B23 SLOT_SRQ
A22 +5V STB
A21 +9V
B21 +9V
A19 +5V
+5V
B19
A15 LVDS_TX9+
A14 LVDS_TX9-
A13 LVDS_TX8+
A12 LVDS_TX8-
A10 LVDS_TX7+
A9 LVDS_TX7-
A8 LVDS_TX6+
A7 LVDS_TX6-
A5 LVDS_TX5+
A4 LVDS_TX5-
B12 LVDS_TXC+
B11 LVDS_TXC-
A3 LVDS_TX4+
A2 LVDS_TX4-
B15 LVDS_TX3+
B14 LVDS_TX3-
B9 LVDS_TX2+
B8 LVDS_TX2-
B6 LVDS_TX1+
B5 LVDS_TX1-
B3 LVDS_TX0+
B2 LVDS_TX0-
FOR
FACTORY
H2
USE
1 EPCS_DCLK
2 GND
3 CONFIG DONE
4 +3.3V
5
6 FPGA_NCE
7 EPCS_DATA
8 EPCS_NCS
9 EPCS_ASD
10 RESET