Aiwa XD-DV290K Service Manual page 52

Pin No. Pin Name
173 DAI-BCK
174 P109
175 CLKSEL
176 A_VDD
177 VCLK
178 SYSCLK
179 A-VSS
DVD-DATA0/CD-
180
DATA
181 VDD
DVD-DATA1/CD-
182
LRCK
183 VSS
DVD-DATA2/CD-
184
BCK
DVD-DATA3/CD-
185
C2PO
DVD-DATA4/
186-189
CDG_SDATA
190 PI101
191 VREQUEST
192 VSTROBE
193 VDD
194 AREQUEST
195 VSS
196 V-DACK/ASTROBE
197 VDD
I/O
I PCM input bit clock.
I/O Programmable I/O pins.
I Clock Select: Internal = VDD, External = VSS
— 3.3-V analog supply voltage.
I Video clock. Clocks out data on input. VDATA [7:0]. Clock is typically 27 MHz.
System clock. Decoderrequires an external 27MHz TTL oscillator. Drive with the
I
same 27-MHz as VCK.
— Analog ground for PLL.
Serial CD data. This pin is shared with DVD compressed data DVD-DATA0. ERROR
I 200 I Error in input data. If ERROR signal is not available from the DSP it must be
grounded.
— 3.3-V supply voltage for I/O signals.
Programmable polarity 16-bit word synchronization to the decoder (right channel
I
HIGH). This pin is shared with DVD compressed data DVD-DATA1.
— Ground for core logic and I/O signals.
CD bit clock. Decoder acceptmultipleBCKrates. This pin is shared with DVD
I
compressed data DVD-DATA2.
Asserted HIGH indicates a corrupted byte. Decoder keeps the previous valid picture
I on-screen until the next valid picture is decoded. This pin is shared with DVD
compressed data DVD-DATA3.
DVD parallel compressed data from DVD DSP. When DVD DSP sends 32-bit words,
it must write the
DVD-DATA5/CDG_VFSY
DVD-DATA6/CDG_SOSI
I
DVD-DATA7/CDG_SCLK
frame-start or composite synchronization input. CDG-S0S1: CD+G (Subcode) Block
Sync. Indicates block-start synchronization input. CDG-SCLK: CD+G (Subcode)
Clock. Indicates subcode data clock input or out-put.
I/O Programmable I/O pins.
Video request. Decoder asserts VREQUEST to indicate that the video input buffer has
O
available space. Polarity is programmable.
Video strobe. Programmable dual mode pulse. Asynchronous and synchronous. In
I Asynchronous mode, anexternal sourcepulses VSTROBE to indicate data is ready for
transfer. In synchronous mode VSTROBE clocks data.
— 3.3-V supply voltage for I/O signals.
Audio request. Decoder asserts AREQUEST to indicate that the audio input buffer has
O
available space. (Not used.)
— Ground for core logic and I/O signals.
In synchronous mode, Video data acknowledge. Asserted when DVD data is valid.
I Polarity is programmable. In asynchronous mode, data strobing for audio bit stream
input.
— 2.5-V supply voltage for core logic.
66
Description
MSB first. CDG-SDATA: CD+G (Subcode) Data.
Indicates serial subcode data input.
CDG-VSFY: CD+G (Subcode) Frame Sync. Indicates