Aiwa XD-DV290K Service Manual page 46

Pin No. Pin Name
29, 30 ALPHA0, 1
31-36 OSD0-5
37 GND
38 VDD
39, 40 OSD6 ,7
41 AGND
42 DACF
43 DACE
44 DACD
45 VBIAS2
46 VAA
47 COMP2
48 FSADJ2
49 VREF
50 N/C
51 AGND
52 VAA
53 FSADJ1
54 COMP1
55 VAA
56 VBIAS1
57 DACC
58 DACB
59 DACA
60 AGND
61 GND
62 ALTADDR
I/O
"Alpha blend pins. Provides for 1-, 2-, or 4-bit external blend selection" between video
I and graphic overlay data. Signals are latched using the system clock. (Connected to
GND.)
Dedicated graphic overlay port. Pixel data (TTL compatible) in 8-bit YCrCb format.
I
Signals are latched using the system clock. (Connected to GND.)
— Digital ground.
— Digital power.
Dedicated graphic overlay port. Pixel data (TTL compatible) in 8-bit YCrCb format.
I
Signals are latched using the system clock. (Connected to GND.)
— Analog ground.
O Component chrominance U channel, component blue, or composite video.
O Component chrominance V channel, component green, or composite video.
O "Component luminance, component red, or optional luma-delayed" composite video.
AGND; the capacitor must be as close to the device as possible to keep lead lengths to
an absolute minimum.
Analog power.
This pin to VAA. The capacitor must be as close to the device as possible to keep lead
lengths to an absolute minimum. COMP1 is used with DACs A/B/C and COMP2 is
used with DACs D/E/F.
Full-scale adjust control pin. Resistors RSET1 and RSET2 connected between these
pins and AGND controls the full-scale output current on the "analog outputs. For
I
standard operation, use the nominal values shown" under Recommended Operating
Conditions. FSADJ2 controls DACs D/E/F.
O Voltage reference pin.
— Not used.
— Analog ground.
— Analog power.
Full-scale adjust control pin. Resistors RSET1 and RSET2 connected between these
pins and AGND controls the full-scale output current on the "analog outputs. For
I
standard operation, use the nominal values shown" under Recommended Operating
Conditions. FSADJ1 controls DACs A/B/C.
O Compensation pin.
— Analog power.
— DAC bias voltage.
O Composite video.
O Modulated chrominance video signal or optional luma-delayed composite video.
O Luminance video or optional composite video.
— Analog ground.
— Digital ground.
Alternate slave address input (TTL compatible). A logical 1 corresponds to "write
address of 0x88 and a read address of 0x89, while a logical 0" corresponds to a write
I
address of 0x8A and a read address of 0x8B. See the Serial Programming Interface
section for more detail. (Connected to GND.)
60
Description