Aiwa XD-DV290K Service Manual page 48

IC, CL61330
Pin No. Pin Name
1 P100
2-4 HDATA0-2
5 VDD_3.3
6 HDATA3
7 VSS
8-11 HDATA4-7
12 VDD_2.5
13 RESET
14 VSS
15 /WAIT
16 /INT
17 VDD
18 /AMWE
19 VSS
20
21-26 HDATA8-13
27 VDD
28 HDATA14
29 VSS
30 HDATA15
31-35 HADDR12-16
36 VDD
37 HADDR17
38 VSS
39 HADDR18
40 VDD
41 HADDR19
42 VSS
43-46 HADDR20-23
I/O
I/O Programmable I/O pins.
8-bit bi-directional host data bus. Host writes data to the decoder Code FIFO via
I/O HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes
the decoder internal registers and local SDRAM/ROM via HDATA [7:0].
— 3.3-V supply voltage for I/O signals.
8-bit bi-directional host data bus. Host writes data to the decoder Code FIFO via
I/O HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes
the decoder internal registers and local SDRAM/ROM via HDATA [7:0].
— Ground for core logic and I/O signals.
8-bit bi-directional host data bus. Host writes data to the decoder Code FIFO via
I/O HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes
the decoder internal egisters and local SDRAM/ROM via HDATA [7:0].
— 2.5-V supply voltage for core logic.
Hardware reset. An external device asserts RESET (activeLOW) to execute a decoder
I hardware reset. " To ensure proper initialization after power is stable, assert RESET
for at least 20 ms."
— Ground for core logic and I/O signals.
Transfer not complete/data acknowledge. Active LOW to indicate host initiated
transfer is not complete. WAIT is asserted after the falling edge of CS and
O
reassertedwhendecoderis ready to "complete transfer cycle. Open drain signal," must
be pulled-up via 1kW to 3.3 volts. Driven high for 10 ns before tristate.
"Host interrupt. Open drain signal, must be pulled-up via 4.7kW to 3.3 volts. Driven
O
high for" 10 ns before tristate.
— 3.3-V supply voltage for I/O signals.
— Not used.
— Ground for core logic and I/O signals.
I/O Programmable I/O pins. Input mode after reset.
— 3.3-V supply voltage for I/O signals.
I/O Programmable I/O pins. Input mode after reset.
— Ground for core logic and I/O signals.
I/O Programmable I/O pins. Input mode after reset.
I/O Programmable I/O pins. Output mode after reset.
— 3.3-V supply voltage for I/O signals.
I/O Programmable I/O pins. Output mode after reset.
— Ground for core logic and I/O signals.
I/O Programmable I/O pins. Output mode after reset.
— 2.5-V supply voltage for core logic.
I/O Programmable I/O pins. Output mode after reset.
— Ground for core logic and I/O signals.
I/O Programmable I/O pins. Output mode after reset.
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Description