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Pin No.
Pin Name
47
VDD
48
BEO
49
VSS
50, 51
NC
52
P101
53, 54
MDATA15, 0
55
VDD
56
MDATA14
57
VSS
58-60
MDATA1, 13, 2
61
VDD_3.3
62
MDATA12
63
VSS
64
MDATA3
65
VDD
66
MDATA11
67
VSS
68
MDATA4
69
VDD
70
MDATA10
71
VSS
72-74
MDATA5, 9, 6
75
VDD
76
MDATA8
77
VSS
78
MDATA7
79
LDQM
80
UDQM
81
VDD
82
/MWE
83
VSS
84
SD-CLK
85
/SD-CAS
86
/SD-RAS
87
VDD
88
SD-CS1
89
VSS
90
SD-CS0
91
VDD
92
NC
I/O
—
3.3-V supply voltage for I/O signals.
I/O
Programmable I/O pins. Output mode after reset.
—
Ground for core logic and I/O signals.
O
No Connection
I/O
Programmable I/O pins.
I/O
Memory data.
—
3.3-V supply voltage for I/O signals.
I/O
Memory data.
—
Ground for core logic and I/O signals.
I/O
Memory data.
—
3.3-V supply voltage for I/O signals.
I/O
Memory data.
—
Ground for core logic and I/O signals.
I/O
Memory data.
—
2.5-V supply voltage for core logic.
I/O
Memory data.
—
Ground for core logic and I/O signals.
I/O
Memory data.
—
3.3-V supply voltage for I/O signals.
I/O
Memory data.
—
Ground for core logic and I/O signals.
I/O
Memory data.
—
3.3-V supply voltage for I/O signals.
I/O
Memory data.
—
Ground for core logic and I/O signals.
I/O
Memory data.
O
SDRAM LDQM.
O
SDRAM UDQM.
—
3.3-V supply voltage for I/O signals.
SDRAM write enable. Decoder asserts active LOW to request a write operation to the
O
SDRAM array.
—
Ground for core logic and I/O signals.
O
SDRAM system clock.
O
Active LOW SDRAM column address.
O
Active LOW SDRAM row address.
—
3.3-V supply voltage for I/O signals.
O
Active LOW SDRAM bank select.
—
Ground for core logic and I/O signals.
O
Active LOW SDRAM bank select.
—
2.5-V supply voltage for core logic.
O
No Connection.
63
Description
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