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Pin No.
Pin Name
63
RESET
64
VDD
65
GND
66
PGND
67
XTI
68
XTO
69
VPLL
70
CLKO
71
CLKIN
72
VIDFIELD
73
TTXREQ
74
TTXDAT
75
SID
76
SIC
77
GND
78
VDD
79, 80
VID0, 1
I/O
Reset control input (TTL compatible). Setting to zero resets both video "timing
(horizontal, vertical, subcarrier counters to the start of VSYNC of" "first field) and the
I
serial control interface, and resets the registers. RESET" must be a logical 1 for normal
operation.
—
Digital power. Refer to the PC Board Considerations section of this
—
Digital ground.
—
Dedicated ground for PLL.
I
Crystal input for genlock PLL. (Not used.)
O
Crystal output for genlock PLL. (Not used.)
—
Dedicated power supply for PLL. (Connected to VDD.)
2x pixel clock for the primary video port. Generated by PLL or pass-through from
O
CLKIN pin. (Not used.)
I
2x pixel clock input (TTL compatible).
Field indicator for video input port. A logical 1 indicates data is from an odd field. The
I
sense of this signal is controlled by the VIDFIELDI bit of register 0x1C. (Connected to
GND.)
O
Teletext request output (TTL compatible). (Connected to VDD.)
I
Teletext bit stream input (TTL compatible). (Connected to GND.)
Serial interface data input/output (TTL compatible). Data is written to and read from
I/O
the device via this serial bus.
I
Serial interface clock input (TTL compatible). The maximum clock rate is 400 kHz.
—
Digital ground.
—
Digital power.
Secondary video input port. Pixel data (TTL compatible) in 8-bit YCrCb format. A
I
higher index corresponds to a greater bit significance. Data on the VID port is latched
by rising edge of VIDCLK. (Connected to GND.)
61
Description
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