Atari 400 Technical Reference Manual page 90

nonzero to zero then an indirect JSR is performed via CDTMAl
(0226,2].
Stage 2 VBLANK Process
The stage 2 VB LANK processing per~orms the ~ollowing for those
VB LANK interrupts that do not interrupt critical sections:
The stage 2 VBLANK process clears the 6502 processor I bit.
This enables the IRQ interrupts.
The stage 2 VB LANK process updates various hardware
registers with data from the OS data base, as shown below:
Data Base Hardware Reason for Update
Item Register
SDLSTH [0231] DLISTH [D403] Display list start
SDLSTL (0230] DLISTL (D402]
SDMCTL [022F] DMACTL [D400]
CHBAS
[02F4]
CHBASE [D409]
CHACT
[02F3] CHACTL [D401]
GPRIOR [026F]
PRIOR
[0018]
COLORO [02C4] COLPFO [0016]
Attract mode.
COLOR 1 (02C5] COLPFl (0017]
COLOR2 (02C63 COLPF2 [0018]
COLOR3 [02C7] COLPF3 [D019]
COLOR4 [02CS]
COLBK
[DOIA]
PCOLRO [02CO] COLPMO [00123
PCOLRl [02Cl]
COLPMl [D013]
PCOLR2 [02C2] COLPM2 [0014]
PCOLR3 [02C3]
COLPM3 [0015]
Constant
=
8
CONSOL [DOIF] Console speaker off.
The stage 2 VBLANK process decrements the System Timer 2
CDTMV2 [021A,2] i~ it is nonzero; if the timer goes from
nonzero to zero, then an indirect JSR is performed
through COTMA2 [0228,2].
The stage 2 VBLAMK process decrements System Timers
3,
4 and
5 i~ they are nonzero; the corresponding flags are set to
zero for each timer that changes from nonzero to zero.
OPERATING SYSTEM C016555 -- Section 6
105