Interrupt System - Atari 400 Technical Reference Manual

D. INTERRUPT SYSTEM
There are two basic types of interrupts defined on the microprocessor:
NMI (non maskable interrupt) and IRQ (interrupt request). It is recommended
that a thorough understanding of these interrupt types be acquired by
reading all chapters concerning interrupts in the 6502 microprocessor
programming and hardware manuals.
In this system NMI interrupts are used for video display and reset.
IRQ interrupts are used for serial port communication, peripheral devices,
timers, and keyboard inputs.
NMI Interrupts: Even though NMI interrupts are "unmaskable" on
the micrprocessor, this system has interrupt enable (mask) bits for NMI
function. (Bits 6 and 7 of NMIEN) When these bits are zero NMI interrupts
are disabled (masked) and prevented from causing a microprocessor NMI
interrupt. (see NMIEN register description) The 3 types of NMI interrupts
are:
1.
D7
2. D6
3. D5
Instruction Interrupt (during display time any display
instruction with bit 7=1 will cause this interrupt to occur
(if enabled) at the start of the last video line displayed by
that instruction.)
Vertical Blank Interrupt (interrupt occurs (if enabled) at
the beginning of the vertical blank time interval.)
Reset Button Interrupt (pushing the SYSTEM RESET button will
cause this interrupt to occur.)
Since any of these interrupts will cause the processor to jump to the
same NMI address, the system also has NMI status bits which may be examined
by the processor to determine which source caused the NMI interrupt. Bits
5, 6, and 7 of NMIST serve this function (see NMIST register description).
These status bits are set by the corresponding interrupt function (even if
the interrupt is masked from the processor by NMIEN). The status bits may
be reset together by writing to the address NMIRES.
Two of the interrupt enable bits (bits 6 and 7 of NMIEN) are cleared
automatically during system power turn on and therefore these NMI interrupts
are initially disabled (masked), preventing any power turn on service routine
from being interrupted before proper initialization of registers and pointers.*
They can then be enabled by the processor whenever desired, by writing into
bits 6 and 7 of NMIEN. Except for the reset button interrupt, they can also
be disabled by the processor by writing a zero into bits 6 or 7 or NMIEN.
The reset button cannot be disabled, allowing an unstoppable escape from any
possible "hangup" condition.
These NMI interrupt functions are each separated in time (to prevent
overlaps) and converted to pulses by the system hardware, in order to supply
NMI transitions required by the microprocessor logic.
* - NOTE: Bit 5 is never disabled and therefore the Reset Button
should not be pressed during power turn on.
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