Atari 400 Technical Reference Manual page 474

Control Re ister-Addressed if bit 2 of PBCTL is 0
I I I I I I
Each bit corresponds to a jack pin
O=input
l=output
OS SHADOWS: STICK2 (hex 27A), STICK3 (27B), PTRIG4-7 (280-283)
PBCTL (Port B Control) (D303): This address writes or reads data from
the Port B Control Register.
D7
x
Read Onl:2:
I I I
Port B Control
D6
I
D5
I
D4
I
D3 D2 D1 DO Register
0 1 1 X
X
0
X
Set up register as
shown (X=Described
below)
D7 (Read only) Peripheral B Interrupt Status Bit. Serial
bus Interrupt line. Reset by Reading Port B Register.
Set by Peripheral B Interrupt.
D3 Peripheral Command Identification. Serial bus Command
Line.
D2 Controls Port B addressing described above.
(1= Port B Register 0 = Direction Control Register)
DO Peripheral B Interrupt Enable Bit. 1 = Enable.
Reset by power turn-on or processor. Set by processor.
(Set to hex 3C by OS IRQ code)
POTO - POT7 (Pot Values) (D200-D207): These addresses read the value (0
to 228) of 8 pots (paddle controllers) connected to the 8 lines pot port.
The paddle controllers are numbered from left to right when facing the
console keyboard. Turning the paddle knob clockwise results in decreasing
pot values. The values are valid only after 228 TV lines following the
"POTGO" command described below or after ALLPOT changes.
D7 D6 D5 D4 D3 D2 D1 DO
Each Pot Value (0-228)
OS SHADOWS: PADDLO - 7 (hex 270-277)
111.21