Pokey - Atari 400 Technical Reference Manual

The PAL T.V. has a slower frame rate (50 Hz. instead of 60 Hz.) so
games will be slower unless an adjustment is made. PAL has more T.V.
lines per frame (312 instead of 262). The Atari 800 hardware compensates
for this by adding extra lines at the beginning of vertical blank. Display
lists do not have to be altered. However, their actual vertical height will
be shorter. PAL ATARI 800 colors are similar to NTSC because of a hardware
modification.
B. POKEY
Audio: There are 4 semi-independent audio channels, each with its own
frequency, noise, and volume control. Each has an 8 bit "divide by N"
frequency divider, controlled by an 8 bit register (AUDFX). (See audio-serial
port block diagram.) Each channel also has an 8 bit control register (AUDCX)
which selects the noise (poly counter) content, and the volume.
Frequency Dividers: All 4 frequency dividers can be clocked simultane-
ously from 64 KHZ or 15 KHZ. (AUDCTL bit 0). Frequency dividers 1 and 3
can alternately be clocked from 1.79 MHZ (AUDCTL bits 6 and 5). Dividers 2
and 4 can alternately be clocked with the output of dividers 1 and 3 (AUDCTL
bits 4 and 3). This allows the following options: 4 channels of 8 bits
resolution, 2 channels of 16 bit resolution, or 1 channel of 16 bit and 2
channels of 8 bit.
Poly Noise Counters: There are 3 polynomial counters (17 bit,S bit
and 4 bit) used to generate random noise. The 17 bit poly counter can be
reduced to 9 bits (AUDCTL bit 7). These counters are all clocked by 1.79
MHZ. Their outputs, however, can be sampled independently by the four
audio channels at a rate determined by each channel's frequency divider.
Thus each channel appears to contain separate poly counters (3 types)
clocked at its own frequency. This poly counter noise sampling is controlled
by bits 5,6 and 7 of each AUDCX register. Because the poly counters are
sampled by the "divide by N" frequency divider, the output obviously cannot
change faster than the sampling rate. In these modes (poly noise outputted)
the dividers are therefore acting as "low pass" filter clocks, allowing only
the low frequency noise to pass.
The output of the noise control circuit described above consists of
pure tones (square wave type), or polynomial counter noise at a maximum
frequency set by the "divide by N" counter (low pass clock). This output
can be routed through a high pass filter if desired (AUDCTL bits 1 and
2).
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