Atari 400 Technical Reference Manual page 465

HITCLR (Collision "HIT" Clear) DOlE
This write address clears all collision bits described
above.
F. AUDIO
Not
Used
AUDCTL (Audio Control) (D208): This address writes data into the Audio
Mode Control Register. (Also see SKCTL two-tone bit 3 and notes).
I
D7
I
D6
I
D5
D4 D3 D2 D1 DO
D7 Change 17 bit poly into a 9 bit below poly.
D6 Clock Channell with 1.79 MHZ, instead of 64 KHZ.
D5 Clock Channel 3 with 1.79 MHZ, instead of 64 KHZ.
D4 Clock Channel 2 with Channell, instead of 64 KHZ (16 BIT).
D3 Clock Channel 4 with Channel 3, instead of 64 KHZ (16 BIT).
D2 Insert Hi Pass Filter in Channell, clocked by Channel 3.
(See section II.)
D1 Insert Hi Pass Filter in Channel 2, clocked by Channel 4.
DO Change Normal 64 KHZ frequency, into 15 KHZ.
Exact Frequencies: The frequencies given above are approximate. The
Exact Frequency (fin) that clocks the divide by N counters is given below
(NTSC only, PAL different).
FIN FIN
1.79 MHZ 1.78979 MHZ Use modified formula for fout
64 KHZ 63.9210 KHZ
- Use normal formula for fout
15 KHZ 15.6999 KHZ
The Normal Formula for output frequency is:
Fout Fin/2N
Where N
=
The binary number in the frequency register (AUDF) , plus 1 (N=AUDF+1).
The MODIFIED FORMULA should be
~sed
when Fin
=
1.79 MHZ and a more exact result
is desired:
Where:.
Fout Fin
2(AUDF + M)
M
=
4 if 8 bit counter (AUDCTL bit 3 or 4
=
0)
M
=
7 if 16 bit counter (AUDCTL bit 3 or 4
=
1)
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