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Appendix C — Specifications
Linearity error:
Output ranges:
External Trigger
Trigger threshold:
Hysteresis:
Input load:
Maximum input voltage:
Minimum pulse width:
Microprocessor and Data Communication
Processor:
Memory:
Data communication:
Expansion Ports
2
I
C expansion port:
Digital output:
Digital input:
±1 LSB (from 0 °C to 70 °C)
±200 mV to ±10 V full scale in six steps
± 10 V
± 5 V
± 2 V
± 1 V
± 500 mV
± 200 mV
+2.9 V (TTL compatible)
1.1 V (turns off at +1.8 V)
1 TTL load
±12 V
5 µs
16 MHz 68340
512 K RAM
SCSI (up to 4 megabytes/s, maximum,
dependent on computer)
USB (up to 500 kilobytes/s, maximum
dependent on setup)
Power and control bus for front-end units.
Supports up to 16 front-ends, but limited to
the PowerLab's free connectors. Interface
communications rate of up to 10,000 bits/s.
8 independent lines, TTL output level
(50 mA maximum load per line; 250 mA
maximum total load)
8 independent lines, TTL input level,
threshold 2.2 V
49
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