ADInstruments PowerLab/4SP Owner's Manual page 37

Figure A–2
Block diagram of the
PowerLab/8
SP
Appendix A — Technical Aspects
(analog-to-digital converter). The ADC can sample at up to 200,000
samples per second. The CPU assembles groups of samples into
blocks and then transmits them to the computer, where the
application program receives, records, and displays the data.
Sampled data from the ADC are stored in FIFOs until the CPU is
ready to read them. The FIFOs let the CPU know when they are
getting full, at which point it will read all of their data very quickly.
This frees the CPU from the need to read every sample from the ADC
as it is ready, so that it can perform other tasks.
The external trigger input (marked 'Trigger' on the front panel) is
connected to a comparator circuit that triggers when the input
I 2 C Port
SCSI PORT
I 2 C
Controller
SCSI
Controller
LATCH
LATCH
SYSTEM GLUE
& REAL-TIME
FIFO
CLOCK
SAMPLING
CONTROL
GLUE
Analog Output External Trigger
Analog Output Ext Trigger
USB Port
USB
Controller
ROM
MC68340
RAM
CPU
FIFO
Digital Output Digital Input
FIFO
LATCH
16-BIT ADC
Multiplexer
Analog Input
Analog Input Channels
POWER
SUPPLY
50/60Hz
MAINS
SYNC
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