Aaeon SBC-590 User Manual page 47

By choosing the "CHIPSET FEATURES SETUP" option from the
CMOS SETUP screen menu, the following screen is displayed.
This sample screen contains the manufacturer's default values for
the SBC-590 board.
Auto Configuration
Decoupled Refresh
Relocate 256K/384K
Video BIOS Cacheable
System BIOS Cacheable
External Cache Scheme
Combine Alter & Tag Bits
CHRDY for ISA master
Memory Hole at 15MB Addr. : Disabled
Cache Timing Control
DRAM Timing Control
FAST DRAM
CPU Write Back Cache
Set Turbo pin function
Set Mouse Lock
Internal Flash/ROM Disk
40 SBC-590 User's Manual
ROM ISA BIOS (2C4L6AK1)
CMOS SETUP UTILITY
CHIPSET FEATURES SETUP
: Enabled Onboard local bus IDE
: Enabled
IDE Primary Master PIO
: Disabled
IDE Primary Slave PIO
: Enabled Onboard FDD Controller
: Enabled Onboard Serial Port 1
On-board Serial Port 2
: Write back Infra Red (IR) Function
: Enabled Onboard Parallel Port
: Enabled
Onboard Parallel Mode
: Normal IR Tansfer Mode
: Normal IR I/O Group
: Enabled
Esc : Quit
: Disabled
F1 : Help
: Turbo
F5 : Old Values
: Disabled
F6 : Load BIOS Defaults
: Disabled
F7 : Load Setup Defaults
: Enabled
: Auto
: Auto
: Enabled
: COM1/3F8
: COM2/2F8
: Disabled
: 3BCH/IRQ7
: Normal
: Half-Dup
: B
: Select Item
PU/PD/+/- : Modify
(Shift)F2 : Color