Antennatuner Circuits - Icom IC-7400 Service Manual

4-3-4 3RD LO CIRCUIT (RF UNIT)
The DDS IC (IC1601) generates a 10-bit digital signal using
the 32 MHz system clock. The digital signal is converted into
an analog wave signal at the D/A converter (R1601–R1620).
The converted analog wave is passed through the bandpass
filter (L1602, L1603, L1605, C1609–C1613, C1615–C1617)
and then applied to the MAIN unit as the 3rd LO signal
(491.000 kHz).
4-3-5 MARKER CIRCUIT (RF UNIT)
The signal divided at the DDS circuit (IC1101) is used for the
marker signals.
The reference signal for the DDS circuit (32.0 MHz) is di-
vided by 2 to produce an acceptable frequency signal, 16
MHz, with the programmable divider then divided again by
160 to obtain 100 kHz cycle square-wave signals.
The generated marker signals are output from pin 49 of the
DDS IC (IC1101) and then applied to the 1st mixer circuit
(Q211, Q212) via the marker switch (IC1081) as the MKR
signal.
4-4 ANTENNA TUNER CIRCUITS
4-4-1 MATCHING CIRCUIT (TUNER UNIT)
The matching circuit is a T-network. Using 2 tuning motors,
the matching circuit obtains rapid overall tuning speed.
Using relays (RL1–RL15), the relay control signals from the
antenna tuner CPU (CTRL unit; IC5) via the buffer amplifier
(Q1–Q15) ground one of the taps of L3–L9, L11, L12 and
add capacitors (C34–C43). After selecting the coils and ca-
pacitors, 2 motors (MF1, MF2) adjust C44 and C45 using the
antenna tuner CPU (CTRL unit; IC5) and the motor driver cir-
cuit (CTRL unit; Q211–Q218) to obtain a low SWR (Stand-
ing Wave Ratio).
PLL circuit
ANT
1st mixer
Q211, Q212
RF signal
64.485–238.455 MHz
Q1201
2
Q1221
or
Q1241 1
Q1261
Main loop PLL
1/N divider
Phase
detector
IC1801
64.455 MHz
Crystal
filter
1st LO PLL circuit
IC1101
Phase
detector
1/22
Ref. loop PLL
Q1301
Reference oscillator
X1901: 32.0 MHz
4-4-2 DETECTOR CIRCUITS (CTRL UNIT)
(1) SWR detector
Forward and reflected power are picked up by a current
transformer (L1), detected by D1 and D2, and then amplified
at IC1b and IC1a, respectively. The amplified voltages are
applied to the antenna tuner CPU (IC5, pins 2, 3). The an-
tenna tuner CPU detects the SWR.
(2) Reactance components detector
Reactance components are picked up by comparing the
phases of the RF current and RF voltage. The RF current is
detected by L4 and R16, and rectified at D5. The rectified
current is amplified at the C-MOS inverter amplifier (IC14e)
and buffer amplifier (IC2a). The amplified signal is then ap-
plied to the phase comparator (IC3a).RF voltage is detected
by C12–C14 and rectified at D4. The rectified voltage is am-
plified at the C-MOS inverter amplifier (IC14c) and buffer am-
plifer (IC2b). The amplified signal is then applied to the phase
comparator (IC3b).
The output signal from the phase comparator (IC3a, pin 6 for
RF current, IC3b pin 7 for RF voltage) is rectified at D7 and
D6 for conversion into DC voltage. The rectified voltages are
combined, and amplified at IC4b, then applied to the antenna
tuner CPU (IC5, pin 64).
A C-MOS inverter IC is used for the buffer-amplifier (IC14) to
improve functionable sensitivity. The C-MOS inverter ampli-
fier is very responsive, and ensure quick and stable signal
detection, even at a low RF signal level input.
(3) Resistance components detector
Resistance components are picked up by L8, and detected
by D8, D9 and Q5. The detected resistance components are
amplified at the amplifier (IC4a), and then applied to the an-
tenna tuner CPU (IC5, pin 1).
4-4-3 MOTOR CONTROL CIRCUIT
The control circuit of the internal antenna tuner consists of
the CPU, EEPROM*, tuning motors and tuning relays.
*Electronically-Erasable Programmable Read Only Memory
RF unit
2nd mixer
D261
12 bit
D/A
BPF
DDS
Q1903
2
Q1904
4 - 7
MAIN unit
3rd mixer
IC631
to DSC unit
BPF
D/A
IC1601
DDS