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*ESE
Meaning and Type
Event Status Enable
Device Status
Description
This command programs the Standard Event Status Enable register bits. The programming determines which events of the
Standard Event Status Event register (see *ESR?) are allowed to set the ESB (Event Summary Bit) of the Status Byte
register. A "1" in the bit position enables the corresponding event. All of the enabled events of the Standard Event Status
Event register are logically ORed to cause the Event Summary Bit (ESB) of the Status Byte register to be set. See "Chapter
4 - Status Reporting" for descriptions of all three registers.
Bit Position
Bit Name
PON
128
Bit Weight
CME = Command error; DDE = Device-dependent error; EXE = Execution error;
OPC = Operation complete; PON Power-on; QYE = Query error.
Returned Parameters
Related Commands
If PSC is programmed to 0, then the *ESE command causes a write cycle to nonvolatile memory. The
nonvolatile memory has a finite maximum number of write cycles (see Table A-2, Supplementary
Characteristics). Programs that repeatedly cause write cycles to nonvolatile memory
can eventually exceed the maximum number of write cycles and may cause the memory to fail.
*ESR?
Meaning and Type
Event Status Register
Device Status
Description
This query reads the Standard Event Status Event register. Reading the register clears it. The bit configuration of this
register is the same as the Standard Event Status Enable register (*ESE). See "Chapter 8 - Status Reporting" for a detailed
explanation of this register.
Returned Parameters
Related Commands
Bit Configuration of Standard Event Status Enable Register
7
6
5
0
CME
64
32
Command Syntax
Parameters
Power On Value
Suffix
Example
Query Syntax
Query Syntax
Parameters
4
3
EXE
DDE
QYE
16
8
*ESE <NRf>
0 to 255
(See *PSC)
(None)
*ESE 129
*ESE?
<NR1>
(Register value)
*ESR? *PSC *STB?
*ESR?
(None)
<NR1>
(Register binary value)
*CLS *ESE *ESE? *OPC
2
1
0
0
OPC
4
2
1
Language Dictionary
65
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