Schematic Diagram - Video Bottom - Yamaha RX-Z9 Service Manual

A B C
RX-Z9/DSP-Z9
SCHEMATIC DIAGRAM (VIDEO BOTTOM)
1
9.0
9.0 9.0
1.2
9.2 7.6
7.6
7.6
7.6
0 ~
0.5 0.5 0.5
7.6
0
0
2.2 2.2 0
2
2.2 2.2 3.7
0
0 0 0.1 3.7 0.1
0
4.8 -4.8
-4.8
9.0
3
4
5
4.8
0
6
4.8
-4.8
7
8
Page 141 E-5
Page 141 J-3 or N-3
TO VIDEO TOP CB27 or CB36 TO VIDEO TOP CB13
EUROPRE
9
IC1, 2 : NJM2904M IC11–14 : LA7104M IC3 : TC74HCU04AFEL IC4, 6 : TC74HC4051AFEL
IC8, 115 : OPA2653U 6dB Amp & Driver Hex Inverters IC5, 7 : CD4051BNSR
Dual OP-Amp Analog Multiplexers/Demultiplexers
1A 1 14 V
OUT 1 8 +V VIN1+ 1 16 +VCC DD
1 CC
1Y 2 13 6A
–IN 2 7 OUT A 11
1 2 NFB1 2 6dB DR 15 VOUT1
+ – + –
B 10
2A 3 12 6Y
+IN 1 3 6 –IN 2 C
MUTE1 3 14 GND
VSS
2Y 4 11 5A
–V CC 4 5 +IN 2
VEE
10 VIN2+ VOUT2
4 13 3A 5 10 5Y X0
13
X1
3Y 6 9 4A 14
NFB2 5 6dB DR 12 DR CTL
X2
15
V SS 7 8 4Y
–VCC1 VOUT3 X3
6 11 12
X4
VIN3+ 7 10 MUTE2
X5
NFB3 –VCC2 X6
8 6dB DR 9
X7
142
D E F
4.8
LPF/BUFFER
0
2.9
0
0
0 3.7 2.9
10
2.9
0
COMPONENT
0
VIDEO DECODER
FRQUENCY
COUNTER
0
0
9.0
3.7
11
3.7
2.3
0
9.0 5.4
9.0
5.4
0
VIDEO DECODER
3.7
3.7
0
16M SDRAM
X: NOT USED
IC15 : TC74HC4052AF
Analog Multiplexers/Demultiplexers
INHIBIT VDD
INHIBIT VDD
6 16
6 16
LEVEL BINARY TO 1-OF-8 LEVEL BINARY TO 1-OF-4
A 10
CONVERTER DECODER WITH INHIBIT
CONVERTER DECODER WITH INHIBIT
9 B 9
8 VSS 8
7 VEE 7
SW X0 12 SW
X1 14 SW
SW
INPUT STATES
"ON" CHANNEL (S)
X2 15 SW
SW INHIBIT C B A
0 0 0 0 0
X X3 11
SW 3 1
0 0 0 1
0 0 1 0 2 Y0 1 SW
1 SW
1
0 0 1 3
Y1 5 SW
5 SW 0 1 0 0 4
1 0 1 5
0 Y2 2 SW
2 SW
0 1 1 0 6
0 1 1 1 7 Y3
4 SW 4
1 X X X NONE
G H
3.7
0
3.7
2.9
PLD3
VIDEO
ENCODER
0
3.7
0
0
3.4
3.7
GUI/OSD
PROCESSOR
PLD1
32M ROM
VIDEO CPU
12
0
3.4
IC9, 10 : TC74HC4053AF (EL)
Analog Multiplexers/Demultiplexers
VDD
16
14 X-COMMON
A 11 OUT C IN 12 OX
OUT C IN 13 IX
B 10
OUT C IN 2 OY
OUT C IN 1 IY
13 X CONTROL INPUTS
C 9
OUT C IN 5 OZ INHIBIT C
(Pin 6) (Pin 9)
SW
L L
OUT C IN IZ
3 L L
L L
INH L L
6 4 Z-COMMON
INHIBIT B A L H
3 Y
0 0 0 0x, 0y L H
0 0 1 1x, 1y 15 Y-COMMON L H
0 1 0 2x, 2y L H
SW
0 1 1 3x, 3y H *
1 X X NONE * Don't Care
8 7
VSS VEE
I J K
3.7 3.7 3.7
0 0 0
I/P CONVERTER
ENHANCER
64M SDRAM
32M ROM
4.8
PLD2
Page 131 L-5
TO DSP1 (1) CB8
IC24 : AN13300A
Video Signal Input-Output
Interface for DSP
POST-Y N.C. POST-C POST-C POST-Y POST-Y N.C. PRE-Y CLAMP
OUT CONT OUT GND IN ADJ IN (Capacitor) OUT DC CP
22 21 20 19 18 17 16 15 14 13 12
LPF
DI-CLAMP
GCA NC
LPF
"ON" CHANNEL SW GCA CLAMP LPF CLAMP
DC SHIFTER
B A 0X (Pin 12), 0Y (Pin 2), 0Z (Pin 5)
(Pin 10) (Pin 11) 1X (Pin 13), 1Y (Pin 1), 1Z (Pin 3)
L L 0X, 0Y, 0Z
L H 1X, 0Y, 0Z
SW GCA LPF
H L 0X, 1Y, 0Z
H H 1X, 1Y, 0Z
L L 0X, 0Y, 1Z
L H 1X, 0Y, 1Z
H L 0X, 1Y, 1Z
1 2 3 4 5 6 7 8 9 10 11
H H 1X, 1Y, 1Z
* * NOTE EE-Y EE/VV VV-Y PRE-Y VCC1 EE-C GND VV-C PRE-C VCC2 PRE-C
IN SW IN ADJ IN IN ADJ OUT
L M N
IC34–39 : SN74LVC16244ADGGR
3-State Buffer Driver
4, 10, 15, 21, 28, 34, 39, 45
3.7 3.7
3.7 GND
7, 18, 31, 42
1 VCC
1OE
47 2
1A1 1Y1
46 3
1Y2
1A2
44 5
1A3 1Y3
43 6
1A4 1Y4
48
2OE
41 8
2Y1
2A1
40 9
2A2 2Y2
38 11
2Y3
2A3
12
37
2A4 2Y4
25
3OE
0 0
0
13
36
3A1 3Y1
35 14
3Y2
3A2
33 16
3A3 3Y3
32 17
3A4 3Y4
24
4OE
30 19
4A1 4Y1
20
29 4Y2
4A2
27 22
4A3 4Y3
26 23
4Y4
4A4
INPUTS OUTPUT
Y
OE A
L H H
L L L
H X Z
Point !0 (Pin 82 of IC22)
13
V : 2V/div, H : 20nsec/div
DC, 1 : 1 probe
0V
Point !1 (Pin 9 of IC23)
V : 500mV/div, H : 1µsec/div
DC, 1 : 1 probe
0V
Point !2 (Pin 20 of IC33)
V : 1V/div, H : 100nsec/div
DC, 1 : 1 probe
0V
REGULATOR
4.8 3.0 4.5
3.7
3.8 2.3 4.5 3.7
Point !3 (Pin 191 of IC40)
V : 2V/div, H : 40nsec/div
DC, 1 : 1 probe
0V
IC16 : PQ018EZ01ZP
IC17 : PQ025EZ01ZP
IC18, 19 : PQ033EZ01ZP
Rgulator
DC INPUT (VIN) 1 3 DC OUTPUT (VO)
I C
2 ON/OFF CONTROL (VC)
5
GND
* All voltages are measured with a 10M Ω /V DC electronic volt meter.
* Components having special characteristics are marked Z and
must be replaced with parts having specifications equal to those
originally installed.
* Schematic diagram is subject to change without notice.
O