Schematic Diagram - Dsp2 - Yamaha RX-Z9 Service Manual

A B C
SCHEMATIC DIAGRAM (DSP2)
1
3.3
3.3
4M SRAM
2
0
2.6
0
0
3 3.3
3.3
2.6
0 2.6 0
DSP
3.3
4
2.6 2.6
2.6
0
0 0
2.6
3.3
5
3.3
3.3
4M SRAM
0
6
3.3
2.6
0
0
3.3
2.6
0
0
2.6
7
DSP
3.3
8
2.6 2.6
2.6
0
0
2.6
0
3.3
IC29 : 74LCX02MTCX IC24 : SN74AHC1G08DCKB IC30, 31 : SN74LV573APWR
Quad 2 Input NOR 2 Input AND Gate Octal 3-State D-Latcheds
9
IN B 1 5 VDD OUTPUT
1
CONTROL
14 13 12 11 10 9 8 OE
1D 2
D Q
IN A 2
OE
2D 3
D Q
OE
3D 4 D Q
VSS 3 4 OUT X
OE
4D 5 D Q
1 2 3 4 5 6 7 OE
5D 6 D Q
OE
6D 7 D Q
OE
7D 8 D Q
OE
8D 9 D Q
GND 10
IC20 : SN74AHC2GU04HDCTR IC28 : SN74AHC1G32DCKR
10
Triple Inverters Single 2-Input Positive-OR Gate
Latch
Output
Data Output
Control Enable
L H H H
L H L L
1A 1 8 VCC 1 5 VCC L L X Q
A 0
H X X Z
3Y 2 7 1Y B 2
2A 3 6 3A GND 3 4 Y
GND 4 5 2Y
D E F
Page 131
TO DSP1 (1) CB2
EUROPE
3.3
0
3.3
4M SRAM
4M SRAM
0
2.6
0 0
0
2.6
3.3
2.6
0
2.6
DSP
DSP
3.3
2.6
2.6
0 0
0 0
0
2.6
3.3
3.3
4M SRAM 4M SRAM
0
2.6
0 0
0
2.6
3.3
2.6
2.6 0
DSP
DSP
3.3
2.6
2.6
0 0
0
0
0
2.6
3.3
IC1, 3, 5, 7, 9, 11, 13, 15 : IC23 : MBM29LV160BE-70TN
CY7C1041CV33-12ZCT 16M-Bit Flash ROM
Static RAM
A0 1
44 A17
VCC A1 2 43 A16 A15 1 48 A16
20
A2 3 42 A15
A14 2 47 /BYTE VCC RY/BY
A3 4 41 OE RY/BY
BUFFER
1Q A4 5 40 BHE A13 3 46 VSS VSS
19
CE 6 39 BLE
I/O0 7 A12 4 45 DQ15
38 I/O15
I/O1 8 37 I/O14
18 2Q A11 5 44 DQ17
I/O2 9 36 I/O13
WE
I/O3 10 35 I/O12 A10 6 43 DQ14
BYTE
VCC 11 34 VSS
17 3Q A9 7 42 DQ6
VSS 12 33 VCC RESET CONTROL
I/O4
13 32 I/O11 A8 8 41 DQ13 CIRCUIT
I/O5 14 I/O10
31
16 4Q I/O6 15 30 I/O9 A19 9 40 DQ5 (COMMAND REGISTER)
I/O7 16 29 I/O8
NC 10 39 DQ12 WRITE CIRCUIT
WE 17 28 NC
15 5Q A5 18 27 A14 /WE 11 38 DQ4
A6
19 26 A13
A7 20 A12 /RESET 12 37 VCC CE
25
A8 21 24 A11
14 6Q NC 13 36 DQ11 OE
A9 22 23 A10
NC 14 35 DQ3
13 7Q RY/BY 15 34 DQ10
A18 16 33 DQ2
12 8Q A17 17 32 DQ9
INPUT BUFFER
A7 18 31 DQ1
11
CLOCK A6 19 30 DQ8
A0
A5 20 29 DQ0
A1
WRITE/ERASE
A3 I/O0-I/O7 A4 21 28 /OE LOW VCC DETECT
256K x 16 PULSE TIMER
A4
ARRAY A3 22 27 VSS
A5 1024 x 4086
I/O8-I/O15 A0~A18
A6 A2 23 26 /CE
A7
A1 A0
A8 24 25
A-1
COLUMN
DECODER
BHE
WE
CE
OE
BLE
G H
H-8 Page 131 I-8 Page 131 J-1
TO DSP1 (1) CB3 TO DSP1 (1) CB4
0 0
0
2.0 3.3
2.6
3.3
4M SRAM
0 0
2.6 2.6
0
0 0
2.6
3.3
0
2.6
DSP
3.3
2.6
2.6 2.6
0
0
0 0
2.6 2.6
3.3 3.3
3.3
4M SRAM
0 0
2.6
2.6
0 0
0
2.6
3.3
0
2.6
DSP
3.3
2.6
2.6
2.6
0
0 0
2.6
0
2.6
3.3
3.3
IC27 : W986432DH-7
512K x 4 Banks x 32Bits SDRAM
DQ0~DQ15 CLK
VCC 1 86 VSS CLOCK
DQ0 DQ15 BUFFER
2 85
VCCQ 3 84 VSSQ
DQ1 4 83 DQ14
CKE
DQ2 5 82 DQ13
VSSQ 6 81 VCCQ
DQ3 7 80 DQ12
DQ4 8 79 DQ11
ERASE CIRCUIT I/O BUFFER CS
VCCQ 9 78 VSSQ CONTROL
DQ5 10 77 DQ10 SIGNAL
DQ6 DQ9 GENERATOR
11 76 RAS COMMAND
VSSQ 12 75 VCCQ
DQ7 13 74 DQ8
CAS
NC 14 73 NC DECODER
VCC 15 72 VSS COLUMN DECODER
WE
DQM0 16 71 DQM1
WE 17 70 NC
CAS 18 69 NC
RAS 19 68 CLK
CELL ARRY
CS 20 67 CKE A10 BANK #0
NC 21 66 A9
BS0 A8
22 65
STB BS1 23 64 A7 MODE
CHIP ENABLE DATA LATCH A10/AP 24 63 A6
A0 REGISTER SENSE AMPLIFIER
OUTPUT ENABLE A0 25 62 A5
A1 26 61 A4 ADDRESS
BUFFER
CIRCUIT A2 27 60 A3 A9
DQM2 28 59 DQM3
BS0
VCC 29 58 VSS BS1
NC 30 57 NC
DQ16 DQ31
31 56
VSSQ 32 55 VCCQ
DQ17 33 54 DQ30
DQ18 34 53 DQ29 DATA CONTROL
VCCQ 35 52 VSSQ CIRCUIT
Y DECODER Y GATE DQ19 36 51 DQ28
DQ20 37 50 DQ27
REFRESH COLUMN
VSSQ 38 49 VCCQ COUNTER COUNTER
STB DQ21 39 48 DQ26
DQ22 40 47 DQ25
VCCQ 41 46 VSSQ
DQ23 DQ24
42 45
16,777,216 VCC 43 44 VSS
X DECODER CELL
MATRIX COLUMN DECODER
CELL ARRY
BANK #2
SENSE AMPLIFIER
I J K
0
3.4
3.4
SDRAM
2.6
3.6
4
3.3
0
0
AUDIO DECODER DSP
2.0
2.6
5
0
3.3
0
0 0
IC22 : ADSST-AUDIO7085
DSP Microcomputer
CORE PROCESSOR DUAL-PORTED SRAM
TWO INDEPENDENT
INSTRUCTION
DUAL-PORTED BLOCKS
TIMER CACHE
32 x 48-BIT I/O PORT
PROCESSOR PORT
ADDR DATA DATA ADDR
ADDR DATA DATA ADDR
DAG1 DAG2
PROGRAM
8 x 4 x 32 8 x 4 x 32
SEQUENCER
COLUMN DECODER
IOD IOA
EXTERNAL PORT
64
32 18
CELL ARRY
BANK #1
PM ADDRESS BUS
32
SENSE AMPLIFIER DM ADDRESS BUS
64
BUS MULTIPROCESSOR
DMn PM DATA BUS
CONNECT 64
(PX)
DM DATA BUS
DQ0
DQ
BUFFER
DQ31
DATA DATA
DQM0-3 REGISTER REGISTER
FILE FILE
(PEY) (PEY)
BARREL BARREL
MULT 16 x 40-BIT SHIFTER SHIFTER 16 x 40-BIT
MULT
COLUMN DECODER
CELL ARRY
IOP
BANK #3 CONTROLLER
ALU ALU REGISTERS
(MEMORY MAPPED)
SERIAL PORTS (4)
SENSE AMPLIFIER
CONTROL,
LINK PORTS (2)
STATUS, &
DATA BUFFERS
SPI PORTS (1)
I/O PROCESSOR
L M N
RX-Z9/DSP-Z9
3.4
0
0
ROM
3.4
2.0
0
0
0
8 Point r (Pin 3 of IC20)
Point t (Pin 12 of IC22)
JTAG TEST
AND EMULATION
V : 2V/div, H : 40nsec/div V : 2V/div, H : 20nsec/div
12
GPIO DC, 1 : 1 probe
DC, 1 : 1 probe
FLAGS
8
SDRAM
CONTROLLER
24
ADDR BUS
MUX
0V 0V
INTERFACE
DATA BUS 32
MUX
HOST PORT
5 * All voltages are measured with a 10M Ω /V DC electronic volt meter.
DMA
16
* Components having special characteristics are marked Z and
20
must be replaced with parts having specifications equal to those
4
originally installed.
* Schematic diagram is subject to change without notice.
133