Schematic Diagram - Video Top - Yamaha RX-Z9 Service Manual

A B C
RX-Z9/DSP-Z9
SCHEMATIC DIAGRAM (VIDEO TOP 1/2)
1
-0.1
2
0
14.6
14.4
0.2
13.2
11.8
14.5
0.2
0
14.5 0
0
0
3
-12.5 0
-12.5 0 0 0
0
0
0
0
-12.5 0
0
-12.5 0
0
0 0
0
0
4.8
0
0
4
0
3.6
0
0 0
0 0
0
4.8
4.8
4.7
10.7
4.8
5.2
4.8
4.8
4.8
0.5
0.6
5
0
4.9
4.9
4.9
4.9
4.9
4.9
4.9 4.9
4.9 4.9
4.9
4.9 0
6
0
7
4.9
4.2
4.8
8
9
Page 135 C-1
TO FUNCTION W13
(U, C, A only)
10
140
D E F
4M ROM
0
2.8
2.1
1.7
2.4
2.9
2.0
2.2
2.3
0
0
2.8
2.3
1.7
2.4
2.7
1.8
2.5 1.9
2.8
1.9
0 2.1
1.7
2.4
4.8
0
2.3
0
2.2
4.7
2.0
2.9
2.9
2.0
2.4
2.2
1.7
MAIN CPU
2.3
2.1
0
2.8
4.8
4.8
4.8
4.8
4.8
4.8
4.8
2.2
0
~
0
4.6
4.7
0
4.7 2.4
0
2.4
2.9
4.7
0
4.6
0.5
0.5
0
2.2 0.9
0
~ 0 3.4 0.9 0 4.9
4.7
2.4 0
1.4 4.8
0 0
0 4.9
4.8 0.5
2.9
4.9
0 1.2
4.8 5.2
0.1
12.2 5.2
4.7
12.4
0
17.6
0
4.7 0.1
4.7 9
CH1
0
0
12.0
5.2
13.0
0
6.5
0
7.1
0.7
6.5
0
0
0.7
0 0
0
0 0
TO AM/FM TUNER
Page 144 L-4
(U, C, A only)
TO SUB TRANS (4) W862
G H
3.3 3.4
0
4.7
0
4.9
0.3
4.8
0
0
0
0.5
0.1
0
4.7
4.6
0
1.0
3.5
0
4.7
0
4.9
1.9
4.7
0
0
0
4.7
0
0
0
3.5
4.7
4.7
4.7
4.7
4.7
4.6
0
0
0
0
4.7
0
4.7
0
4.7
4.7
8 4.7 0
0
0
4.7
0
4.7
0
4.8
0
4.7
0
4.8
0
0
9
CH2 1.2
0
RESET
4.7
0
0
0
0
4.8
13.1 5.6
5.6 4.8
3.5
4.8
4.1
13.1
5.6 5.6 4.8
4.1
0.6
0
REGULATOR
I J K
3.3 2.3
4.8
3.7
0.1
4.7
0
4.3
4.7
4.9
-12.4
4.2 4.8
3.5
4.2
4.1 4.8
3.5
4.1
4.4
4.8
4.7
-12.4
4.1 4.8
3.5
4.1
4.4
4.8
4.7
-12.4
4.2 4.8
3.5
4.2
4.8
4.2
3.5
4.2
12.2
0.7
0
0
12.2
0
L M N
Point i (Pin 20 of IC56)
V : 2V/div, H : 100nsec/div
DC, 1 : 1 probe
EUROPE
0V
Point o
CH 1 : Emitter of Q18
CH 2 : Collector of Q19
V : 5V/div (CH 1)
X: NOT USED
V : 5V/div (CH 2)
DC, 1 : 1 probe, H : 4.0sec/div
CH 1
CH 2
↑ ↑
AC POWER OFF
AC POWER ON
(Disconnect the power cable)
(Connect the power cable)
IC49 : SN74AHCT126PW
Quad 3-State Bus Buffers
1C 1 14 Vcc
1A 2 13 4C
1Y 3 12 4A
2C 4 11 4Y
2A 5 10 3C
2Y 6 9 3A
GND 7 8 3Y
IC53 : SN74AHC2GU04HDCTR
Triple Inverters
1A 1 8 VCC
3Y 2 7 1Y
2A 3 6 3A
GND 4 5 2Y
IC50–52 : SN74LV573APWR
Octal 3-State D-Latcheds
OUTPUT
1 20 VCC
CONTROL
OE
1D 2 D Q 19 1Q
OE
2D 3 D Q 18 2Q
OE
3D 4 D Q 17 3Q
OE
4D 5 D Q 16 4Q
OE
5D 6 D Q 15 5Q
OE
6D 7 D Q 14 6Q
OE
8 7Q
7D D Q 13
OE
8D 9 12 8Q
D Q
GND 10 11 CLOCK
Output Latch
Data Output
Control Enable
L H H H
L H L L
L L X Q 0
H X X Z
IC55 : MX29F400BTC-70 IC58 : SN74LV245APWR
4M-Bit CMOS Flash Memory IC59 : SN74AHCT245PWR
Octal 3-State Bus Transceivers
CE DIR 1 20 V
Control Program/Erase Write State
OE
Input Logic High Voltage
Machine (WSM)
WE A1 2 19 ENG
A2 3 18 B1
Address State
Flash
Latch Register
A0~A17 Array
and Array A3 4 17 B2
Buffer Source
HV
A4 5 16 B3
Command
Y-Pass
Data Decoder
Gate
6 15 B4
A5
Command A6 7 14 B5
Sense PGM Data Latch
Amplifier Data HV
8 13 B6
A7
Program
A8 9 12 B7
Data Latch
GND 11 B8
10
Q0~Q15/A-1
I/O Buffer
IC54 : TC74HC4051AFEL
Analog Multiplexers/Demultiplexers
INHIBIT VDD
6 16
A 11
LEVEL BINARY TO 1-OF-8
B 10
CONVERTER
DECODER WITH INHIBIT
C 9
VSS 8
VEE 7
X0
13 SW
X1
14 SW
INPUT STATES
X2 "ON" CHANNEL (S)
15 SW INHIBIT C B A
0 0 0 0
X3 12 SW 3 X
0 0 0 1
X4 1 SW 0 0 1 0
0 0 1 1
X5 5 SW
0 1 0 0
0 1 0 1
X6 2 SW
0 1 1 0
X7 4 SW 0 1 1 1
1 X X X NONE
* All voltages are measured with a 10M Ω /V DC electronic volt meter.
* Components having special characteristics are marked Z and
must be replaced with parts having specifications equal to those
originally installed.
* Schematic diagram is subject to change without notice.
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CC
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